\n

CLK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PWRCON

CLKSEL0

CLKSEL1

CLKDIV

CLKSEL2

PLLCON

FRQDIV

AHBCLK

APBCLK

CLKSTATUS


PWRCON

System Power Down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWRCON PWRCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTL12M_EN OSC22M_EN OSC10K_EN PD_WU_DLY PD_WU_INT_EN PD_WU_STS PWR_DOWN_EN PD_WAIT_CPU

XTL12M_EN : External 4~24 MHz High Speed Crystal enable (write-protected) The bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from external 4~24 MHz high speed crystal, this bit is set to 1 automatically.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

External 4~24 MHz high speed crystal disable

#1 : 1

External 4~24 MHz high speed crystal enable

End of enumeration elements list.

OSC22M_EN : Internal 22.1184 MHz High Speed Oscillator enable (write-protected)\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal 22.1184 MHz high speed oscillator disable

#1 : 1

Internal 22.1184 MHz high speed oscillator enable

End of enumeration elements list.

OSC10K_EN : Internal 10 kHz Low Speed Oscillator enable (write-protected)\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal 10 kHz low speed oscillator disable

#1 : 1

Internal 10 kHz low speed oscillator enable

End of enumeration elements list.

PD_WU_DLY : Enable the wake up delay counter. (write-protected)\nWhen the chip wakes up from power down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable clock cycles delay

#1 : 1

Enable clock cycles delay

End of enumeration elements list.

PD_WU_INT_EN : Power down mode wake Up Interrupt Enable (write-protected)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable. The interrupt will occur when power down mode wake-up

End of enumeration elements list.

PD_WU_STS : Chip power down wake up status flag Set by power down wake up , it indicates that resume from power down mode The flag is set if the GPIO(P0~P4), and UART wakeup Write 1 to clear this bit to zero. Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write

PWR_DOWN_EN : System Power Down Enable Bit (write-protection bit)\nWhen this bit is set to 1, the chip power down mode is enabled and chip power down behavior will depends on the PD_WAIT_CPU bit\n(a) If the PD_WAIT_CPU is 0, then the chip enters power down mode immediately after the PWR_DOWN_EN bit set.\n(b) if the PD_WAIT_CPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters power down mode\nWhen chip wakes up from power down mode, this bit is auto cleared. Users need to set this bit again for next power down.\nWhen in power down mode, external 4~24 MHz high speed crystal and the internal 22.1184 MHz high speed oscillator will be disabled in this mode, but the internal 10 kHz low speed oscillator are not controlled by power down mode.\nWhen in power down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by power down mode, if the peripheral clock source is from internal 10 kHz low speed oscillator.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip operating normally or chip in idle mode because of WFI command

#1 : 1

Chip enter the power down mode instant or wait CPU sleep command WFI

End of enumeration elements list.

PD_WAIT_CPU : This Bit Control the Power Down Entry Condition (write-protection bit)\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip entry power down mode when the PWR_DOWN_EN bit is set to 1

#1 : 1

Chip enter power down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction

End of enumeration elements list.


CLKSEL0

Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSEL0 CLKSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLK_S STCLK_S

HCLK_S : HCLK clock source select. Note: Before clock switching, the related clock sources (both pre-select and new-select) must be turn on The 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b. These bits are protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from external 4~24 MHz high speed crystal clock

#001 : 1

Reserved\nClock source from internal 22.1184 MHz high speed oscillator clock

#010 : 2

Clock source from PLL clock

#011 : 3

Clock source from internal 10 kHz low speed oscillator clock

End of enumeration elements list.

STCLK_S : MCU Cortex_M0 SysTick clock source select. This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from external 4~24 MHz high speed crystal clock

#001 : 1

Reserved\nClock source from internal 22.1184 MHz high speed oscillator clock/2

#010 : 2

Clock source from external 4~24 MHz high speed crystal clock/2

#011 : 3

Clock source from HCLK/2

End of enumeration elements list.


CLKSEL1

Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSEL1 CLKSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_S ADC_S TMR0_S TMR1_S TMR2_S TMR3_S UART_S PWM01_S PWM23_S

WDT_S : WDT clock source select. This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Reserved

#01 : 1

Reserved

#10 : 2

Clock source from HCLK/2048 clock

#11 : 3

Clock source from internal 10 kHz low speed oscillator clock

End of enumeration elements list.

ADC_S : ADC clock source select.\n
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from external 4~24 MHz high speed crystal clock

#01 : 1

Clock source from PLL clock Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.

TMR0_S : TIMER0 clock source select.\n
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from external 4~24 MHz high speed crystal clock

#001 : 1

Reserved\nClock source from internal 22.1184 MHz high speed oscillator clock

#010 : 2

Clock source from HCLK

#011 : 3

Reserved

End of enumeration elements list.

TMR1_S : TIMER1 clock source select.\n
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from external 4~24 MHz high speed crystal clock

#001 : 1

Reserved\nClock source from internal 22.1184 MHz high speed oscillator clock

#010 : 2

Clock source from HCLK

#011 : 3

Reserved

End of enumeration elements list.

TMR2_S : TIMER2 clock source select.\n
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from external 4~24 MHz high speed crystal clock

#001 : 1

Reserved\nClock source from internal 22.1184 MHz high speed oscillator clock

#010 : 2

Clock source from HCLK

#011 : 3

Reserved

End of enumeration elements list.

TMR3_S : TIMER3 clock source select.\n
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from external 4~24 MHz high speed crystal clock

#001 : 1

Reserved\nClock source from internal 22.1184 MHz high speed oscillator clock

#010 : 2

Clock source from HCLK

#011 : 3

Reserved

End of enumeration elements list.

UART_S : UART clock source select.\n
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from external 4~24 MHz high speed crystal clock

#01 : 1

Clock source from PLL clock Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.

PWM01_S : PWM0 and PWM1 clock source select.\nPWM0 and PWM1 uses the same Engine clock source, both of them use the same pre-scalar\n
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from external 4~24 MHz high speed crystal clock

#01 : 1

Reserved

#10 : 2

Clock source from HCLK

#11 : 3

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.

PWM23_S : PWM2 and PWM3 clock source select.\nPWM2 and PWM3 uses the same Engine clock source, both of them use the same pre-scalar\n
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from external 4~24 MHz high speed crystal clock

#01 : 1

Reserved

#10 : 2

Clock source from HCLK

#11 : 3

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.


CLKDIV

Clock Divider Number Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKDIV CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLK_N UART_N ADC_N

HCLK_N : HCLK clock divide number from HCLK clock source\n
bits : 0 - 3 (4 bit)
access : read-write

UART_N : UART clock divide number from UART clock source\n
bits : 8 - 11 (4 bit)
access : read-write

ADC_N : ADC clock divide number from ADC clock source\n
bits : 16 - 23 (8 bit)
access : read-write


CLKSEL2

Clock Source Select Control Register 2
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSEL2 CLKSEL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRQDIV_S PWM45_S PWM67_S

FRQDIV_S : Clock Divider Clock Source Select\n
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from external 4~24 MHz high speed crystal clock

#01 : 1

Reserved

#10 : 2

Clock source from HCLK

#11 : 3

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.

PWM45_S : PWM4 and PWM5 clock source select\nPWM4 and PWM5 used the same Engine clock source, both of them use the same pre-scalar\n
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from external 4~24 MHz high speed crystal clock

#01 : 1

Reserved

#10 : 2

Clock source from HCLK

#11 : 3

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.

PWM67_S : PWM6 and PWM7 clock source select\nPWM6 and PWM7 used the same Engine clock source, both of them use the same pre-scalar\n
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from external 4~24 MHz high speed crystal clock

#01 : 1

Reserved

#10 : 2

Clock source from HCLK

#11 : 3

Clock source from internal 22.1184 MHz high speed oscillator clock

End of enumeration elements list.


PLLCON

PLL Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCON PLLCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FB_DV IN_DV OUT_DV PD BP OE PLL_SRC

FB_DV : PLL Feedback Divider Control Pins
bits : 0 - 8 (9 bit)
access : read-write

IN_DV : PLL Input Divider Control Pins
bits : 9 - 13 (5 bit)
access : read-write

OUT_DV : PLL Output Divider Control Pins
bits : 14 - 15 (2 bit)
access : read-write

PD : Power Down Mode. If set the IDLE bit 1 in PWRCON register, the PLL will enter power down mode too
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in normal mode

#1 : 1

PLL is in power down mode (default)

End of enumeration elements list.

BP : PLL Bypass Control\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in normal mode (default)

#1 : 1

PLL clock output is same as clock input (XTALin)

End of enumeration elements list.

OE : PLL OE (FOUT enable) pin Control\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL FOUT enable

#1 : 1

PLL FOUT is fixed low

End of enumeration elements list.

PLL_SRC : PLL Source Clock Select\n
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL source clock from external 4~24 MHz high speed crystal

#1 : 1

PLL source clock from internal 22.1184 MHz high speed oscillator

End of enumeration elements list.


FRQDIV

Frequency Divider Control Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRQDIV FRQDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSEL DIVIDER_EN

FSEL : Divider Output Frequency Selection Bits\nThe formula of output frequency is\nFin is the input clock frequency\nFout is the frequency of divider output clock\nN is the 4-bit value of FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write

DIVIDER_EN : Frequency Divider Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable Frequency Divider

#1 : 1

Enable Frequency Divider

End of enumeration elements list.


AHBCLK

AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBCLK AHBCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISP_EN EBI_EN

ISP_EN : Flash ISP Controller Clock Enable Control.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

To disable the Flash ISP controller clock

#1 : 1

To enable the Flash ISP controller clock

End of enumeration elements list.

EBI_EN : EBI Controller Clock Enable Control.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the EBI controller clock

#1 : 1

Enable the EBI controller clock

End of enumeration elements list.


APBCLK

APB Devices Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBCLK APBCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_EN TMR0_EN TMR1_EN TMR2_EN TMR3_EN FDIV_EN I2C_EN SPI0_EN SPI1_EN UART0_EN UART1_EN PWM01_EN PWM23_EN PWM45_EN PWM67_EN ADC_EN

WDT_EN : Watchdog Timer Clock Enable. This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable Watchdog Timer Clock

#1 : 1

Enable Watchdog Timer Clock

End of enumeration elements list.

TMR0_EN : Timer0 Clock Enable\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable Timer0 Clock

#1 : 1

Enable Timer0 Clock

End of enumeration elements list.

TMR1_EN : Timer1 Clock Enable\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable Timer1 Clock

#1 : 1

Enable Timer1 Clock

End of enumeration elements list.

TMR2_EN : Timer2 Clock Enable\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable Timer2 Clock

#1 : 1

Enable Timer2 Clock

End of enumeration elements list.

TMR3_EN : Timer3 Clock Enable\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable Timer3 Clock

#1 : 1

Enable Timer3 Clock

End of enumeration elements list.

FDIV_EN : Clock Divider Clock Enable\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable FDIV Clock

#1 : 1

Enable FDIV Clock

End of enumeration elements list.

I2C_EN : I2C Clock Enable \n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable I2C Clock

#1 : 1

Enable I2C Clock

End of enumeration elements list.

SPI0_EN : SPI0 Clock Enable\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable SPI0 Clock

#1 : 1

Enable SPI0 Clock

End of enumeration elements list.

SPI1_EN : SPI1 Clock Enable\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable SPI1 Clock

#1 : 1

Enable SPI1 Clock

End of enumeration elements list.

UART0_EN : UART0 Clock Enable\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable UART0 clock

#1 : 1

Enable UART0 clock

End of enumeration elements list.

UART1_EN : UART1 Clock Enable\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable UART1 clock

#1 : 1

Enable UART1 clock

End of enumeration elements list.

PWM01_EN : PWM_01 Clock Enable\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable PWM01 clock

#1 : 1

Enable PWM01 clock

End of enumeration elements list.

PWM23_EN : PWM_23 Clock Enable\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable PWM23 clock

#1 : 1

Enable PWM23 clock

End of enumeration elements list.

PWM45_EN : PWM_45 Clock Enable\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable PWM45 clock

#1 : 1

Enable PWM45 clock

End of enumeration elements list.

PWM67_EN : PWM_67 Clock Enable\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable PWM67 clock

#1 : 1

Enable PWM67 clock

End of enumeration elements list.

ADC_EN : Analog-Digital-Converter (ADC) Clock Enable\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable ADC clock

#1 : 1

Enable ADC clock

End of enumeration elements list.


CLKSTATUS

Clock Status Monitor Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSTATUS CLKSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTL12M_STB PLL_STB OSC10K_STB OSC22M_STB CLK_SW_FAIL

XTL12M_STB : External 4~24 MHz High Speed Crystal Clock Source Stable Flag (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

External 4~24 MHz high speed crystal clock is not stable or disable

#1 : 1

External 4~24 MHz high speed crystal clock is stable

End of enumeration elements list.

PLL_STB : PLL Clock Source Stable Flag (Read Only)\n
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

PLL clock is not stable or disable

#1 : 1

PLL clock is stable

End of enumeration elements list.

OSC10K_STB : Internal 10 kHz Low Speed Clock Source Stable Flag (Read Only)\n
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal 10 kHz low speed oscillator clock is not stable or disable

#1 : 1

Internal 10 kHz low speed oscillator clock is stable

End of enumeration elements list.

OSC22M_STB : Internal 22.1184 MHz High Speed Clock Source Stable Flag (Read Only)\n
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal 22.1184 MHz high speed oscillator clock is not stable or disable

#1 : 1

Internal 22.1184 MHz high speed oscillator clock is stable

End of enumeration elements list.

CLK_SW_FAIL : Clock Switch Fail Flag\nThis bit will be set when target switch clock source is not stable. \nWrite 1 to clear this bit to zero.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock switch if success

#1 : 1

Clock switch if fail

End of enumeration elements list.



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