Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0xA0 byte (0x0)
mem_usage : registers
protection : not protected
P0 Pin I/O Mode Control
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMD0 : Px I/O Pin[n] Mode Control
Determine each I/O type of Px pins
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px [n] pin is in INPUT mode
#01 : 1
Px [n] pin is in OUTPUT mode
#10 : 2
Px [n] pin is in Open-Drain mode
#11 : 3
Px [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD1 : Px I/O Pin[n] Mode Control
Determine each I/O type of Px pins
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px [n] pin is in INPUT mode
#01 : 1
Px [n] pin is in OUTPUT mode
#10 : 2
Px [n] pin is in Open-Drain mode
#11 : 3
Px [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD2 : Px I/O Pin[n] Mode Control
Determine each I/O type of Px pins
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px [n] pin is in INPUT mode
#01 : 1
Px [n] pin is in OUTPUT mode
#10 : 2
Px [n] pin is in Open-Drain mode
#11 : 3
Px [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD3 : Px I/O Pin[n] Mode Control
Determine each I/O type of Px pins
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px [n] pin is in INPUT mode
#01 : 1
Px [n] pin is in OUTPUT mode
#10 : 2
Px [n] pin is in Open-Drain mode
#11 : 3
Px [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD4 : Px I/O Pin[n] Mode Control
Determine each I/O type of Px pins
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px [n] pin is in INPUT mode
#01 : 1
Px [n] pin is in OUTPUT mode
#10 : 2
Px [n] pin is in Open-Drain mode
#11 : 3
Px [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD5 : Px I/O Pin[n] Mode Control
Determine each I/O type of Px pins
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px [n] pin is in INPUT mode
#01 : 1
Px [n] pin is in OUTPUT mode
#10 : 2
Px [n] pin is in Open-Drain mode
#11 : 3
Px [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD6 : Px I/O Pin[n] Mode Control
Determine each I/O type of Px pins
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px [n] pin is in INPUT mode
#01 : 1
Px [n] pin is in OUTPUT mode
#10 : 2
Px [n] pin is in Open-Drain mode
#11 : 3
Px [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD7 : Px I/O Pin[n] Mode Control
Determine each I/O type of Px pins
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
Px [n] pin is in INPUT mode
#01 : 1
Px [n] pin is in OUTPUT mode
#10 : 2
Px [n] pin is in Open-Drain mode
#11 : 3
Px [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
P0 Pin Value
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIN0 : Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n
bits : 0 - 0 (1 bit)
access : read-only
PIN1 : Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n
bits : 1 - 1 (1 bit)
access : read-only
PIN2 : Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n
bits : 2 - 2 (1 bit)
access : read-only
PIN3 : Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n
bits : 3 - 3 (1 bit)
access : read-only
PIN4 : Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n
bits : 4 - 4 (1 bit)
access : read-only
PIN5 : Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n
bits : 5 - 5 (1 bit)
access : read-only
PIN6 : Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n
bits : 6 - 6 (1 bit)
access : read-only
PIN7 : Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n
bits : 7 - 7 (1 bit)
access : read-only
P4 Pin I/O Mode Control
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Bit OFF Digital Enable
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Data Output Value
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Data Output Write Mask
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Pin Value
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 De-bounce Enable
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Interrupt Mode Control
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Interrupt Enable
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Interrupt Source Flag
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 De-bounce Enable
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBEN0 : Px Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function is disabled
#1 : 1
The bit[n] de-bounce function is enabled
End of enumeration elements list.
DBEN1 : Px Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function is disabled
#1 : 1
The bit[n] de-bounce function is enabled
End of enumeration elements list.
DBEN2 : Px Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function is disabled
#1 : 1
The bit[n] de-bounce function is enabled
End of enumeration elements list.
DBEN3 : Px Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function is disabled
#1 : 1
The bit[n] de-bounce function is enabled
End of enumeration elements list.
DBEN4 : Px Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function is disabled
#1 : 1
The bit[n] de-bounce function is enabled
End of enumeration elements list.
DBEN5 : Px Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function is disabled
#1 : 1
The bit[n] de-bounce function is enabled
End of enumeration elements list.
DBEN6 : Px Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function is disabled
#1 : 1
The bit[n] de-bounce function is enabled
End of enumeration elements list.
DBEN7 : Px Input Signal De-bounce Enable
DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bit[n] de-bounce function is disabled
#1 : 1
The bit[n] de-bounce function is enabled
End of enumeration elements list.
P0 Interrupt Mode Control
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMD0 : Port 0-4 Interrupt Mode Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD1 : Port 0-4 Interrupt Mode Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD2 : Port 0-4 Interrupt Mode Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD3 : Port 0-4 Interrupt Mode Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD4 : Port 0-4 Interrupt Mode Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD5 : Port 0-4 Interrupt Mode Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD6 : Port 0-4 Interrupt Mode Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD7 : Port 0-4 Interrupt Mode Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
External Interrupt De-bounce Control
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBCLKSEL : De-bounce sampling cycle selection\n
bits : 0 - 3 (4 bit)
access : read-write
DBCLKSRC : De-bounce counter clock source select\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
De-bounce counter clock source is the HCLK
#1 : 1
De-bounce counter clock source is the internal 10kHz low speed oscillator clock
End of enumeration elements list.
ICLK_ON : Interrupt clock On mode
Set this bit 0 will disable the interrupt generate circuit clock, if the pin[n] interrupt is disabled
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable the clock if the P0/1/2/3/4[n] interrupt is disabled
#1 : 1
interrupt generated circuit clock always enable
End of enumeration elements list.
P0 Interrupt Enable
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IF_EN0 : Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IF_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Px[n] state low-level or high-to-low change interrupt
#1 : 1
Enable the Px[n] state low-level or high-to-low change interrupt
End of enumeration elements list.
IF_EN1 : Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IF_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Px[n] state low-level or high-to-low change interrupt
#1 : 1
Enable the Px[n] state low-level or high-to-low change interrupt
End of enumeration elements list.
IF_EN2 : Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IF_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Px[n] state low-level or high-to-low change interrupt
#1 : 1
Enable the Px[n] state low-level or high-to-low change interrupt
End of enumeration elements list.
IF_EN3 : Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IF_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Px[n] state low-level or high-to-low change interrupt
#1 : 1
Enable the Px[n] state low-level or high-to-low change interrupt
End of enumeration elements list.
IF_EN4 : Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IF_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Px[n] state low-level or high-to-low change interrupt
#1 : 1
Enable the Px[n] state low-level or high-to-low change interrupt
End of enumeration elements list.
IF_EN5 : Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IF_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Px[n] state low-level or high-to-low change interrupt
#1 : 1
Enable the Px[n] state low-level or high-to-low change interrupt
End of enumeration elements list.
IF_EN6 : Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IF_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Px[n] state low-level or high-to-low change interrupt
#1 : 1
Enable the Px[n] state low-level or high-to-low change interrupt
End of enumeration elements list.
IF_EN7 : Port 0-4 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IF_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Px[n] state low-level or high-to-low change interrupt
#1 : 1
Enable the Px[n] state low-level or high-to-low change interrupt
End of enumeration elements list.
IR_EN0 : Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IR_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Px[n] level-high or low-to-high interrupt
#1 : 1
Enable the Px[n] level-high or low-to-high interrupt
End of enumeration elements list.
IR_EN1 : Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IR_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Px[n] level-high or low-to-high interrupt
#1 : 1
Enable the Px[n] level-high or low-to-high interrupt
End of enumeration elements list.
IR_EN2 : Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IR_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Px[n] level-high or low-to-high interrupt
#1 : 1
Enable the Px[n] level-high or low-to-high interrupt
End of enumeration elements list.
IR_EN3 : Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IR_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Px[n] level-high or low-to-high interrupt
#1 : 1
Enable the Px[n] level-high or low-to-high interrupt
End of enumeration elements list.
IR_EN4 : Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IR_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Px[n] level-high or low-to-high interrupt
#1 : 1
Enable the Px[n] level-high or low-to-high interrupt
End of enumeration elements list.
IR_EN5 : Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IR_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Px[n] level-high or low-to-high interrupt
#1 : 1
Enable the Px[n] level-high or low-to-high interrupt
End of enumeration elements list.
IR_EN6 : Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IR_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Px[n] level-high or low-to-high interrupt
#1 : 1
Enable the Px[n] level-high or low-to-high interrupt
End of enumeration elements list.
IR_EN7 : Port 0-4 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function
When set the IR_EN[n] bit 1 :
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Px[n] level-high or low-to-high interrupt
#1 : 1
Enable the Px[n] level-high or low-to-high interrupt
End of enumeration elements list.
P0 Interrupt Source Flag
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISRC0 : Port 0-4 Interrupt Trigger Source Indicator
Read :
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Px[n]\nNo action
#1 : 1
Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC1 : Port 0-4 Interrupt Trigger Source Indicator
Read :
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Px[n]\nNo action
#1 : 1
Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC2 : Port 0-4 Interrupt Trigger Source Indicator
Read :
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Px[n]\nNo action
#1 : 1
Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC3 : Port 0-4 Interrupt Trigger Source Indicator
Read :
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Px[n]\nNo action
#1 : 1
Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC4 : Port 0-4 Interrupt Trigger Source Indicator
Read :
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Px[n]\nNo action
#1 : 1
Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC5 : Port 0-4 Interrupt Trigger Source Indicator
Read :
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Px[n]\nNo action
#1 : 1
Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC6 : Port 0-4 Interrupt Trigger Source Indicator
Read :
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Px[n]\nNo action
#1 : 1
Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC7 : Port 0-4 Interrupt Trigger Source Indicator
Read :
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Px[n]\nNo action
#1 : 1
Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
GPIO P0.n Pin Data Input/Output
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Pxn_PDIO : GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set corresponding GPIO pin to low
#1 : 1
Set corresponding GPIO pin to high
End of enumeration elements list.
GPIO P0.n Pin Data Input/Output
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P0.n Pin Data Input/Output
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P0.n Pin Data Input/Output
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P0.n Pin Data Input/Output
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P0.n Pin Data Input/Output
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P0.n Pin Data Input/Output
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P0.n Pin Data Input/Output
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.n Pin Data Input/Output
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.n Pin Data Input/Output
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.n Pin Data Input/Output
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.n Pin Data Input/Output
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.n Pin Data Input/Output
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.n Pin Data Input/Output
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.n Pin Data Input/Output
address_offset : 0x238 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.n Pin Data Input/Output
address_offset : 0x23C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.n Pin Data Input/Output
address_offset : 0x240 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.n Pin Data Input/Output
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.n Pin Data Input/Output
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.n Pin Data Input/Output
address_offset : 0x24C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.n Pin Data Input/Output
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.n Pin Data Input/Output
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.n Pin Data Input/Output
address_offset : 0x258 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.n Pin Data Input/Output
address_offset : 0x25C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.n Pin Data Input/Output
address_offset : 0x260 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.n Pin Data Input/Output
address_offset : 0x264 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.n Pin Data Input/Output
address_offset : 0x268 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.n Pin Data Input/Output
address_offset : 0x26C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.n Pin Data Input/Output
address_offset : 0x270 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.n Pin Data Input/Output
address_offset : 0x274 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.n Pin Data Input/Output
address_offset : 0x278 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.n Pin Data Input/Output
address_offset : 0x27C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.n Pin Data Input/Output
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.n Pin Data Input/Output
address_offset : 0x284 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.n Pin Data Input/Output
address_offset : 0x288 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.n Pin Data Input/Output
address_offset : 0x28C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.n Pin Data Input/Output
address_offset : 0x290 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.n Pin Data Input/Output
address_offset : 0x294 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.n Pin Data Input/Output
address_offset : 0x298 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.n Pin Data Input/Output
address_offset : 0x29C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 Bit OFF Digital Enable
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFD : OFFD: Px Pin[n] OFF digital input path Enable\n
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : 0
Enable IO digital input path
1 : 1
Disable IO digital input path (digital input tied to low)
End of enumeration elements list.
P1 Pin I/O Mode Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Bit OFF Digital Enable
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Data Output Value
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Data Output Write Mask
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Pin Value
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 De-bounce Enable
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Interrupt Mode Control
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Interrupt Enable
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Interrupt Source Flag
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 Data Output Value
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT0 : Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px Pin[n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
Px Pin[n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT1 : Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px Pin[n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
Px Pin[n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT2 : Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px Pin[n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
Px Pin[n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT3 : Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px Pin[n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
Px Pin[n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT4 : Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px Pin[n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
Px Pin[n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT5 : Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px Pin[n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
Px Pin[n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT6 : Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px Pin[n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
Px Pin[n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT7 : Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px Pin[n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
Px Pin[n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
P2 Pin I/O Mode Control
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Bit OFF Digital Enable
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Data Output Value
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Data Output Write Mask
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Pin Value
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 De-bounce Enable
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Interrupt Mode Control
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Interrupt Enable
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Interrupt Source Flag
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 Data Output Write Mask
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMASK0 : Px Data Output Write Mask
These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding Px_DOUT[n] bit is not masked
#1 : 1
The corresponding Px_DOUT[n] bit is masked
End of enumeration elements list.
DMASK1 : Px Data Output Write Mask
These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding Px_DOUT[n] bit is not masked
#1 : 1
The corresponding Px_DOUT[n] bit is masked
End of enumeration elements list.
DMASK2 : Px Data Output Write Mask
These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding Px_DOUT[n] bit is not masked
#1 : 1
The corresponding Px_DOUT[n] bit is masked
End of enumeration elements list.
DMASK3 : Px Data Output Write Mask
These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding Px_DOUT[n] bit is not masked
#1 : 1
The corresponding Px_DOUT[n] bit is masked
End of enumeration elements list.
DMASK4 : Px Data Output Write Mask
These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding Px_DOUT[n] bit is not masked
#1 : 1
The corresponding Px_DOUT[n] bit is masked
End of enumeration elements list.
DMASK5 : Px Data Output Write Mask
These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding Px_DOUT[n] bit is not masked
#1 : 1
The corresponding Px_DOUT[n] bit is masked
End of enumeration elements list.
DMASK6 : Px Data Output Write Mask
These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding Px_DOUT[n] bit is not masked
#1 : 1
The corresponding Px_DOUT[n] bit is masked
End of enumeration elements list.
DMASK7 : Px Data Output Write Mask
These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DMASK bit[n] to 1 , the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding Px_DOUT[n] bit is not masked
#1 : 1
The corresponding Px_DOUT[n] bit is masked
End of enumeration elements list.
P3 Pin I/O Mode Control
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Bit OFF Digital Enable
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Data Output Value
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Data Output Write Mask
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Pin Value
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 De-bounce Enable
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Interrupt Mode Control
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Interrupt Enable
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Interrupt Source Flag
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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