PPR

CMR0

PDR0

CNR1

CMR1

PDR1

CNR2

CMR2

PDR2

CNR3

CMR3

PDR3

CSR

PIER

PIIR

CCR0

CCR2

CRLR0

CFLR0

CRLR1

CFLR1

CRLR2

CFLR2

CRLR3

CFLR3

CAPENR

POE

PCR

CNR0

CP01 : Clock prescaler 0 (PWM counter 0/1 for group A and PWM counter 4/ 5 for group B) Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter
bits : 0 - 7 (8 bit)
access : read-write

CP23 : Clock prescaler 2 (PWM counter 2/ 3 for group A and PWM counter 6/ 7 for group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter\n
bits : 8 - 15 (8 bit)
access : read-write

DZI01 : Dead zone interval register for pair of channel 0 and channel 1 (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from corresponding CSR bits.
bits : 16 - 23 (8 bit)
access : read-write

DZI23 : Dead zone interval register for pair of channel2 and channel3 (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from corresponding CSR bits.
bits : 24 - 31 (8 bit)
access : read-write

CMRx : PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write to CMR will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

PDRx : PWM Data Register\nUser can monitor PDR to know the current value in 16-bit down counter.
bits : 0 - 15 (16 bit)
access : read-only

CSR0 : Timer 0 Clock Source Selection (PWM timer 0 for group A and PWM timer 4 for group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3)
bits : 0 - 2 (3 bit)
access : read-write

CSR1 : Timer 1 Clock Source Selection (PWM timer 1 for group A and PWM timer 5 for group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3)
bits : 4 - 6 (3 bit)
access : read-write

CSR2 : Timer 2 Clock Source Selection (PWM timer 2 for group A and PWM timer 6 for group B)\nSelect clock input for PWM timer.\n(Table is the same as CSR3)
bits : 8 - 10 (3 bit)
access : read-write

CSR3 : Timer 3 Clock Source Selection (PWM timer 3 for group A and PWM timer 7 for group B)\n
bits : 12 - 14 (3 bit)
access : read-write

PWMIE0 : PWM channel 0 Interrupt Enable\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMIE1 : PWM channel 1 Interrupt Enable\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMIE2 : PWM channel 2 Interrupt Enable\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMIE3 : PWM channel 3 Interrupt Enable\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMIF0 : PWM channel 0 Interrupt Status\nFlag is set by hardware when PWM0 down counter reaches zero, software can clear this bit by writing a one to it.
bits : 0 - 0 (1 bit)
access : read-write

PWMIF1 : PWM channel 1 Interrupt Status\nFlag is set by hardware when PWM1 down counter reaches zero, software can clear this bit by writing a one to it.
bits : 1 - 1 (1 bit)
access : read-write

PWMIF2 : PWM channel 2 Interrupt Status\nFlag is set by hardware when PWM2 down counter reaches zero, software can clear this bit by writing a one to it.
bits : 2 - 2 (1 bit)
access : read-write

PWMIF3 : PWM channel 3 Interrupt Status\nFlag is set by hardware when PWM3 down counter reaches zero, software can clear this bit by writing a one to it.
bits : 3 - 3 (1 bit)
access : read-write

INV0 : PWM Group Channel 0 Inverter ON/OFF\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE0 : PWM Group Channel 0 Rising Latch Interrupt Enable ON/OFF\nWhen Enable, if Capture detects PWM group channel 0 has rising transition, Capture issues an Interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE0 : PWM Group Channel 0 Falling Latch Interrupt Enable ON/OFF\nWhen Enable, if Capture detects PWM group channel 0 has falling transition, Capture issues an Interrupt.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH0EN : Capture Channel 0 transition Enable/Disable\nWhen Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF0 : Capture0 Interrupt Indication Flag\n
bits : 4 - 4 (1 bit)
access : read-write

CRLRI0 : CRLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware. \nClear this bit by writing a one to it.
bits : 6 - 6 (1 bit)
access : read-write

CFLRI0 : CFLR0 Latched Indicator Bit\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nClear this bit by writing a one to it.
bits : 7 - 7 (1 bit)
access : read-write

INV1 : PWM Group Channel 1 Inverter ON/OFF\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE1 : PWM Group Channel 1 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 1 has rising transition, Capture issues an Interrupt.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE1 : PWM Group Channel 1 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 1 has falling transition, Capture issues an Interrupt.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH1EN : Capture PWM Group Channel 1 transition Enable/Disable\nWhen Enable, Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF1 : Capture1 Interrupt Indication Flag\n
bits : 20 - 20 (1 bit)
access : read-write

CRLRI1 : CRLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nClear this bit by writing a one to it.
bits : 22 - 22 (1 bit)
access : read-write

CFLRI1 : CFLR1 Latched Indicator Bit\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nClear this bit by writing a one to it.
bits : 23 - 23 (1 bit)
access : read-write

INV2 : PWM Group Channel 2 Inverter ON/OFF\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE2 : PWM Group Channel 2 Rising Latch Interrupt Enable ON/OFF\nWhen Enable, if Capture detects PWM group channel 2 has rising transition, Capture issues an Interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE2 : PWM Group Channel 2 Falling Latch Interrupt Enable ON/OFF\nWhen Enable, if Capture detects PWM group channel 2 has falling transition, Capture issues an Interrupt.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH2EN : Capture Channel 2 transition Enable/Disable\nWhen Enable, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF2 : Capture2 Interrupt Indication Flag\nNote: Write 1 to clear this bit to zero.
bits : 4 - 4 (1 bit)
access : read-write

CRLRI2 : CRLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to zero.
bits : 6 - 6 (1 bit)
access : read-write

CFLRI2 : CFLR2 Latched Indicator Bit\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to zero.
bits : 7 - 7 (1 bit)
access : read-write

INV3 : PWM Group Channel 3 Inverter ON/OFF\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE3 : PWM Group Channel 3 Rising Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 3 has rising transition, Capture issues an Interrupt.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE3 : PWM Group Channel 3 Falling Latch Interrupt Enable\nWhen Enable, if Capture detects PWM group channel 3 has falling transition, Capture issues an Interrupt.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH3EN : Capture Channel 3 transition Enable/Disable\nWhen Enable, Capture latched the PMW-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen Disable, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF3 : Capture3 Interrupt Indication Flag\nWrite 1 to clear this bit to zero.
bits : 20 - 20 (1 bit)
access : read-write

CRLRI3 : CRLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to zero.
bits : 22 - 22 (1 bit)
access : read-write

CFLRI3 : CFLR3 Latched Indicator Bit\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nWrite 1 to clear this bit to zero.
bits : 23 - 23 (1 bit)
access : read-write

CRLRx : Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.
bits : 0 - 15 (16 bit)
access : read-only

CFLRx : Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition.
bits : 0 - 15 (16 bit)
access : read-only

CAPENR : Capture Input Enable Register There are four capture inputs from pad. Bit0~Bit3 are used to control each inputs ON or OFF. CAPENR Bit 3210 for PWM group A Bit xxx1 ( Capture channel 0 is from P2.0 Bit xx1x ( Capture channel 1 is from P2.1 Bit x1xx ( Capture channel 2 is from P2.2 Bit 1xxx ( Capture channel 3 is from P2.3 Bit 3210 for PWM group B Bit xxx1 ( Capture channel 0 is from P2.4 Bit xx1x ( Capture channel 1 is from P2.5 Bit x1xx ( Capture channel 2 is from P2.6 Bit 1xxx ( Capture channel 3 is from P2.7
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0 : PWM Channel 0 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1 : PWM Channel 1 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM2 : PWM Channel 2 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM3 : PWM Channel 3 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0EN : PWM-Timer 0 Enable/Disable Start Run (PWM timer 0 for group A and PWM timer 4 for group B)\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0INV : PWM-Timer 0 Output Inverter ON/OFF (PWM timer 0 for group A and PWM timer 4 for group B)\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0MOD : PWM-Timer 0 Auto-reload/One-Shot Mode (PWM timer 0 for group A and PWM timer 4 for group B)\nNote: If there is a rising transition at this bit, it will cause CNR0 and CMR0 be clear.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DZEN01 : Dead-Zone 0 Generator Enable/Disable (PWM0 and PWM1 pair for PWM group A, PWM4 and PWM5 pair for PWM group B)\nNote: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DZEN23 : Dead-Zone 2 Generator Enable/Disable (PWM2 and PWM3 pair for PWM group A, PWM6 and PWM7 pair for PWM group B)\nNote: When Dead-Zone Generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1EN : PWM-Timer 1 Enable/Disable Start Run (PWM timer 1 for group A and PWM timer 5 for group B)\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1INV : PWM-Timer 1 Output Inverter ON/OFF (PWM timer 1 for group A and PWM timer 5 for group B)\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1MOD : PWM-Timer 1 Auto-reload/One-Shot Mode (PWM timer 1 for group A and PWM timer 5 for group B)\nNote: If there is a rising transition at this bit, it will cause CNR1 and CMR1 be clear.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2EN : PWM-Timer 2 Enable/Disable Start Run (PWM timer 2 for group A and PWM timer 6 for group B)\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2INV : PWM-Timer 2 Output Inverter ON/OFF (PWM timer 2 for group A and PWM timer 6 for group B)\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2MOD : PWM-Timer 2 Auto-reload/One-Shot Mode (PWM timer 2 for group A and PWM timer 6 for group B)\nNote: If there is a rising transition at this bit, it will cause CNR2 and CMR2 be clear.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH3EN : PWM-Timer 3 Enable/Disable Start Run (PWM timer 3 for group A and PWM timer 7 for group B)\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH3INV : PWM-Timer 3 Output Inverter ON/OFF (PWM timer 3 for group A and PWM timer 7 for group B)\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH3MOD : PWM-Timer 3 Auto-reload/One-Shot Mode (PWM timer 3 for group A and PWM timer 7 for group B)\nNote: If there is a rising transition at this bit, it will cause CNR3 and CMR3 be clear.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNRx : PWM Counter/Timer Loaded Value\nCNR determines the PWM period.\nNote: Any write to CNR will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write