Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GO_BUSY : Go and Busy Status\nDuring the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNOTE: All registers should be set before writing 1 to this GO_BUSY bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit to stop data transfer if SPI is transferring
#1 : 1
In master mode, writing 1 to this bit to start the SPI data transfer in slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
End of enumeration elements list.
RX_NEG : Receive At Negative Edge\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The received data input signal is latched at the rising edge of SPICLK
#1 : 1
The received data input signal is latched at the falling edge of SPICLK
End of enumeration elements list.
TX_NEG : Transmit At Negative Edge\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transmitted data output signal is changed at the rising edge of SPICLK
#1 : 1
The transmitted data output signal is changed at the falling edge of SPICLK
End of enumeration elements list.
TX_BIT_LEN : Transmit Bit Length\nThis field specifies how many bits are transmitted in one transaction. Up to 32 bits can be transmitted.\n
bits : 3 - 7 (5 bit)
access : read-write
TX_NUM : Numbers of Transmit/Receive Word \nThis field specifies how many transmit/receive word numbers should be executed in one transfer.\nNote: in slave mode with level-trigger configuration, if TX_NUM is set to 01, the slave select pin must be kept at active state during the successive data transfer.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Only one transmit/receive word will be executed in one transfer
#01 : 1
Two successive transmit/receive word will be executed in one transfer
#10 : 2
Reserved
#11 : 3
Reserved
End of enumeration elements list.
LSB : LSB First\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the TX_BIT_LEN field)
#1 : 1
The LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position in the RX register (bit 0 of SPI_RX0/1)
End of enumeration elements list.
CLKP : Clock Polarity\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPICLK idle low
#1 : 1
SPICLK idle high
End of enumeration elements list.
SP_CYCLE : Suspend Interval (Master Only)\n
bits : 12 - 15 (4 bit)
access : read-write
IF : Interrupt Flag\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
It indicates that the transfer dose not finish yet
#1 : 1
It indicates that the transfer is done
End of enumeration elements list.
IE : Interrupt Enable\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SPI Interrupt
#1 : 1
Enable SPI Interrupt
End of enumeration elements list.
SLAVE : Slave Mode Indication\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
REORDER : Reorder Mode Select\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\n2. In slave mode with level-trigger configuration, if the byte suspend function is enabled, the slave select pin must be kept at active state during the successive four bytes transfer.
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#00 : 0
Disable both Byte Reorder and byte suspend functions
#01 : 1
Enable Byte Reorder function and insert a byte suspend interval (2~17 serial clock cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word)
#10 : 2
Enable Byte Reorder function, but disable byte suspend function
#11 : 3
Disable Byte Reorder function, but insert a suspend interval (2~17 serial clock cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word)
End of enumeration elements list.
VARCLK_EN : Variable Clock Enable (Master Only)\nNote that when enable this VARCLK_EN bit, the setting of TX_BIT_LEN must be programmed as 0x10 (16 bits mode)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The serial clock output frequency is fixed and decided only by the value of DIVIDER
#1 : 1
The serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2
End of enumeration elements list.
Data Receive Register 0
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register. For example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. The values of the other bits are unknown.\nNOTE: The Data Receive Registers are read only registers.
bits : 0 - 31 (32 bit)
access : read-only
Data Receive Register 1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Transmit Register 0
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register. \nFor example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the SPI controller will perform two 32-bit transmit/receive successive using the same setting. The transmission sequence is TX0[31:0] first and then TX1[31:0].
bits : 0 - 31 (32 bit)
access : write-only
Data Transmit Register 1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Variable Clock Pattern Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VARCLK : Variable Clock Pattern \nThe value in this field is the frequency patterns of the SPI clock. If the bit pattern of VARCLK is '0', the output frequency of SPICLK is according the value of DIVIDER. If the bit patterns of VARCLK are '1', the output frequency of SPICLK is according the value of DIVIDER2. Refer to register SPI_DIVIDER.\nRefer to Figure 651 for Variable Clock timing diagram.
bits : 0 - 31 (32 bit)
access : read-write
Clock Divider Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER : Clock Divider Register (master only)\nThe value in this field is the frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIn slave mode, the period of SPI clock driven by a master shall equal or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK.
bits : 0 - 15 (16 bit)
access : read-write
DIVIDER2 : Clock Divider 2 Register (master only)\nThe value in this field is the 2nd frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIf VARCLK_EN is cleared to 0, this setting is unmeaning.
bits : 16 - 31 (16 bit)
access : read-write
Slave Select Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSR : Slave Select Register (Master only)
If AUTOSS bit is cleared, writing 1 to this bit sets the SPISSx line to an active state and writing 0 sets the line back to inactive state.
If AUTOSS bit is set, writing 0 to this bit will keep the SPISSx line at inactive state writing 1 to this bit will select the SPISSx line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active state of SPISSx is specified in SS_LVL).
Note: SPISSx is always defined as slave select input in slave mode.
bits : 0 - 0 (1 bit)
access : read-write
SS_LVL : Slave Select Active Level \nIt defines the active state of slave select signal (SPISS0/1).\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The slave select signal SPISS0/1 is active at low-level/falling-edge
#1 : 1
The slave select signal SPISS0/1 is active at high-level/rising-edge
End of enumeration elements list.
AUTOSS : Automatic Slave Select (Master only)\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
If this bit is cleared, slave select signal will be asserted and de-asserted by setting and clearing SSR[0]
#1 : 1
If this bit is set, SPISS0/1 signal will be generated automatically. It means that device/slave select signal, which is set in SSR[0], will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished
End of enumeration elements list.
SS_LTRIG : Slave Select Level Trigger (Slave only)\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The input slave select signal is edge-trigger. This is the default value. It depends on SS_LVL to decide the signal is active at falling-edge or rising-edge
#1 : 1
The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high
End of enumeration elements list.
LTRIG_FLAG : Level Trigger Flag\nWhen the SS_LTRIG bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not.\nNote: This bit is READ only
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transaction number or the transferred bit length of one transaction does not meet the specified requirements
#1 : 1
The transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN
End of enumeration elements list.
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