\n

TIMER

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TCSR2

TCSR3

TCMPR3

TISR3

TDR3

TCMPR2

TISR2

TDR2


TCSR2

Timer2 Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCSR2 TCSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESCALE TDR_EN CACT CRST MODE IE CEN DBGACK_TMR

PRESCALE : Pre-scale Counter\n
bits : 0 - 7 (8 bit)
access : read-write

TDR_EN : Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value. \n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer Data Register update disable

#1 : 1

Timer Data Register update enable

End of enumeration elements list.

CACT : Timer Active Status Bit (Read only)\nThis bit indicates the status of timer.\n
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

#0 : 0

Timer is not active

#1 : 1

Timer is active

End of enumeration elements list.

CRST : Timer Reset Bit\nSet this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0.\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Reset Timer's 8-bit pre-scale counter, internal 24-bit up-timer and CEN bit

End of enumeration elements list.

MODE : Timer Operating Mode\n
bits : 27 - 28 (2 bit)
access : read-write

IE : Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated timer is equal to TCMPR.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable timer Interrupt

#1 : 1

Enable timer Interrupt

End of enumeration elements list.

CEN : Timer Enable Bit\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Stops/Suspends counting

#1 : 1

Starts counting

End of enumeration elements list.

DBGACK_TMR : ICE debug mode acknowledge Disable (write-protected)\nTIMER counter will be held while ICE debug mode acknowledged.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

ICE debug mode acknowledgement effects TIMER counting

#1 : 1

ICE debug mode acknowledgement disabled

End of enumeration elements list.


TCSR3

Timer3 Control and Status Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCSR3 TCSR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TCMPR3

Timer3 Compare Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCMPR3 TCMPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TISR3

Timer3 Interrupt Status Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TISR3 TISR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TDR3

Timer3 Data Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDR3 TDR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TCMPR2

Timer2 Compare Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCMPR2 TCMPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCMP

TCMP : Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP.
bits : 0 - 23 (24 bit)
access : read-write


TISR2

Timer2 Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TISR2 TISR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF

TIF : Timer Interrupt Flag\nThis bit indicates the interrupt status of Timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit.
bits : 0 - 0 (1 bit)
access : read-write


TDR2

Timer2 Data Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TDR2 TDR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDR

TDR : Timer Data Register\nWhen TCSR.TDR_EN is set to 1, the internal 24-bit up-timer value will be loaded into TDR. User can read this register for the up-timer value.
bits : 0 - 23 (24 bit)
access : read-only



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