\n

WDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WTCR


WTCR

Watchdog Timer Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR WTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WTR WTRE WTRF WTIF WTWKE WTWKF WTIE WTE WTIS DBGACK_WDT

WTR : Clear Watchdog Timer (write-protection bit)\nSet this bit will clear the Watchdog timer.\nNote: This bit will auto clear after few clock cycle
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writing 0 to this bit has no effect

#1 : 1

Reset the contents of the Watchdog timer

End of enumeration elements list.

WTRE : Watchdog Timer Reset Enable\nSetting this bit will enable the Watchdog timer reset function.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable Watchdog timer reset function

#1 : 1

Enable Watchdog timer reset function

End of enumeration elements list.

WTRF : Watchdog Timer Reset Flag\nWhen the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If WTRE is disabled, then the Watchdog timer has no effect on this bit.\nNote: Write 1 to clear this bit to zero.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer reset did not occur

#1 : 1

Watchdog timer reset occurs

End of enumeration elements list.

WTIF : Watchdog Timer Interrupt Flag\nIf the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. \nNote: This bit is cleared by writing 1 to this bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer interrupt did not occur

#1 : 1

Watchdog timer interrupt occurs

End of enumeration elements list.

WTWKE : Watchdog Timer Wake-up Function Enable bit (write-protection bit)\nNote: Chip can wake-up by WDT only if WDT clock source select RC10K
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable Watchdog timer wake-up chip function

#1 : 1

Enable the Wake-up function that Watchdog timer timeout can wake-up chip from power down mode

End of enumeration elements list.

WTWKF : Watchdog Timer Wake-up Flag\nIf Watchdog timer causes chip wakes up from power down mode, this bit will be set to high. It must be cleared by software with a write 1 to this bit.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer does not cause chip wake-up

#1 : 1

Chip wake-up from idle or power down mode by Watchdog timeout

End of enumeration elements list.

WTIE : Watchdog Timer Interrupt Enable (write protection bits)
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Watchdog timer interrupt

#1 : 1

Enable the Watchdog timer interrupt

End of enumeration elements list.

WTE : Watchdog Timer Enable (write protection bits)
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Watchdog timer (This action will reset the internal counter)

#1 : 1

Enable the Watchdog timer

End of enumeration elements list.

WTIS : Watchdog Timer Interval Select (write protection bits)
bits : 8 - 10 (3 bit)
access : read-write

DBGACK_WDT : ICE debug mode acknowledge Disable (write-protected)\nWatchdog Timer counter will keep going no matter ICE debug mode acknowledged or not.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

ICE debug mode acknowledgement effects Watchdog Timer counting

#1 : 1

ICE debug mode acknowledgement disabled

End of enumeration elements list.



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