UA_RBR

UA_THR

UA_MCR

UA_MSR

UA_FSR

UA_ISR

UA_TOR

UA_BAUD

UA_IRCR

UA_ALT_CSR

UA_FUN_SEL

UA_IER

UA_FCR

UA_LCR

RBR : Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first).
bits : 0 - 7 (8 bit)
access : read-only

THR : Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first).
bits : 0 - 7 (8 bit)
access : write-only

RTS : RTS (Request-To-Send) Signal \n1: Drive RTS pin to logic 1 (If the LEV_RTS set to high level triggered).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LEV_RTS : RTS Trigger Level\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTS_ST : RTS Pin State (Read Only)\nThis bit is the output pin status of RTS.
bits : 13 - 13 (1 bit)
access : read-only

DCTSF : Detect CTS State Change Flag (Read Only) \nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when UA_IER [MODEM_IEN] is set to 1.\nNOTE: This bit is read only, but can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-only

CTS_ST : CTS Pin Status (Read Only)\nThis bit is the pin status of CTS.
bits : 4 - 4 (1 bit)
access : read-only

LEV_CTS : CTS Trigger Level\nThis bit can change the CTS trigger level to send TX_FIFO data.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS_485_ADD_DETF : RS-485 Address Byte Detection Flag (Read Only) \nNote: This field is used for RS-485 function mode.\nNOTE: This bit is read only, but can be cleared by writing '1' to it.
bits : 3 - 3 (1 bit)
access : read-only

PEF : Parity Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit. NOTE: This bit is read only, but can be cleared by writing '1' to it.
bits : 4 - 4 (1 bit)
access : read-only

FEF : Framing Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit. NOTE: This bit is read only, but can be cleared by writing '1' to it.
bits : 5 - 5 (1 bit)
access : read-only

BIF : Break Interrupt Flag (Read Only) This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit. NOTE: This bit is read only, but can be cleared by writing '1' to it.
bits : 6 - 6 (1 bit)
access : read-only

RX_POINTER : RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.
bits : 8 - 13 (6 bit)
access : read-only

RX_EMPTY : Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
bits : 14 - 14 (1 bit)
access : read-only

RX_OVER : Receiver FIFO Over (Read Only)\nThis bit indicates RX FIFO overrunning or not.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 15 bytes of UART0/UART1, this bit will be set. Otherwise is cleared by hardware.
bits : 15 - 15 (1 bit)
access : read-only

TX_POINTER : TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.
bits : 16 - 21 (6 bit)
access : read-only

TX_EMPTY : Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
bits : 22 - 22 (1 bit)
access : read-only

TX_FULL : Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TX_POINTER is equal to16(UART0/UART1), otherwise is cleared by hardware.
bits : 23 - 23 (1 bit)
access : read-only

TX_OVER_IF : TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. \nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 24 - 24 (1 bit)
access : read-only

TE_FLAG : Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
bits : 28 - 28 (1 bit)
access : read-only

RDA_IF : Receive Data Available Interrupt Flag (Read Only).\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDA_IF will be set. If UA_IER [RDA_IEN] is enabled, the RDA interrupt will be generated. \nNOTE: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
bits : 0 - 0 (1 bit)
access : read-only

THRE_IF : Transmit Holding Register Empty Interrupt Flag (Read Only). \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If UA_IER [THRE_IEN] is enabled, the THRE interrupt will be generated.\nNOTE: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
bits : 1 - 1 (1 bit)
access : read-only

RLS_IF : Receive Line Interrupt Flag (Read Only). This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If UA_IER [RLS_IEN] is enabled, the RLS interrupt will be generated. NOTE: Write 1 to clear this bit to zero.
bits : 2 - 2 (1 bit)
access : read-only

MODEM_IF : MODEM Interrupt Flag (Read Only)\nNOTE: Write 1 to clear this bit to zero.
bits : 3 - 3 (1 bit)
access : read-only

TOUT_IF : Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC. If UA_IER [TOUT_IEN] is enabled, the Tout interrupt will be generated. \nNOTE: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
bits : 4 - 4 (1 bit)
access : read-only

BUF_ERR_IF : Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF or RX_OVER_IF is set). When BUF_ERR_IF is set, the transfer maybe is not correct. If UA_IER [BUF_ERR_IEN] is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TX_OVER_IF and RX_OVER_IF are cleared.
bits : 5 - 5 (1 bit)
access : read-only

RDA_INT : Receive Data Available Interrupt Indicator To Interrupt Controller (Read Only).\nAn AND output with inputs of RDA_IEN and RDA_IF
bits : 8 - 8 (1 bit)
access : read-only

THRE_INT : Transmit Holding Register Empty Interrupt Indicator To Interrupt Controller (Read Only).\nAn AND output with inputs of THRE_IEN and THRE_IF
bits : 9 - 9 (1 bit)
access : read-only

RLS_INT : Receive Line Status Interrupt Indicator To Interrupt Controller (Read Only). \nAn AND output with inputs of RLS_IEN and RLS_IF
bits : 10 - 10 (1 bit)
access : read-only

MODEM_INT : MODEM Status Interrupt Indicator To Interrupt Controller (Read Only). \nAn AND output with inputs of MODEM_IEN and MODEM_IF
bits : 11 - 11 (1 bit)
access : read-only

TOUT_INT : Time Out Interrupt Indicator To Interrupt Controller (Read Only)\nAn AND output with inputs of RTO_IEN and TOUT_IF
bits : 12 - 12 (1 bit)
access : read-only

BUF_ERR_INT : Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN and BUF_ERR_IF are both set to 1.\n
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOIC : Time Out Interrupt Comparator\n
bits : 0 - 6 (7 bit)
access : read-write

DLY : TX Delay time value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit.
bits : 8 - 15 (8 bit)
access : read-write

BRD : Baud Rate Divider \nThe field indicated the baud rate divider
bits : 0 - 15 (16 bit)
access : read-write

DIVIDER_X : Divider X\n
bits : 24 - 27 (4 bit)
access : read-write

DIV_X_ONE : Divider X equal 1\nRefer to the Table 610 for more information.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIV_X_EN : Divider X Enable\nRefer to the Table 610 for more information.\nNOTE: When in IrDA mode, this bit must disable.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_SELECT : TX_SELECT\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV_TX : INV_TX\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV_RX : INV_RX\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS_485_NMM : RS-485 Normal Multi-drop Operation Mode (NMM)\nNote: It can't be active with RS-485_AAD operation mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS_485_AAD : RS-485 Auto Address Detection Operation Mode (AAD) \nNote: It can't be active with RS-485_NMM operation mode.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS_485_AUD : RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS_485_ADD_EN : RS-485 Address Detection Enable\nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDR_MATCH : Address match value register\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
bits : 24 - 31 (8 bit)
access : read-write

FUN_SEL : Function Select Enable\n
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDA_IEN : Receive Data Available Interrupt Enable.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

THRE_IEN : Transmit Holding Register Empty Interrupt Enable\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLS_IEN : Receive Line Status Interrupt Enable \n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODEM_IEN : Modem Status Interrupt Enable \n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTO_IEN : RX Time Out Interrupt Enable\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKE_EN : UART Wake-up Function Enable\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIME_OUT_EN : Time Out Counter Enable\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_RTS_EN : RTS Auto Flow Control Enable\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the UA_FCR [RTS_TRI_LEV], the UART will de-assert RTS signal.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_CTS_EN : CTS Auto Flow Control Enable\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RFR : RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFR : TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RFITL : RX FIFO Interrupt (INT_RDA) Trigger Level\n
bits : 4 - 7 (4 bit)
access : read-write

RX_DIS : Receiver Disable register.\nThe receiver is disabled or not (set 1 is disable receiver)\n1: Disable Receiver\n0: Enable Receiver\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before UA_ALT_CSR [RS-485_NMM] is programmed.
bits : 8 - 8 (1 bit)
access : read-write

RTS_TRI_LEV : RTS Trigger Level for Auto-flow Control Use \n
bits : 16 - 19 (4 bit)
access : read-write

WLS : Word Length Select\n
bits : 0 - 1 (2 bit)
access : read-write

NSB : Number of STOP bit Two STOP bit is generated when 6-, 7- and 8-bit word length is selected.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBE : Parity Bit Enable\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPE : Even Parity Enable\nThis bit has effect only when bit 3 (parity bit enable) is set.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPE : Stick Parity Enable\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BCB : Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write