ADDR0

ADDR4

ADDR5

ADDR6

ADDR7

ADCR

ADCHER

ADCMPR0

ADCMPR1

ADSR

ADCALR

ADDR1

ADDR2

ADDR3

RSLT : A/D Conversion Result\nThis field contains conversion result of ADC.
bits : 0 - 11 (12 bit)
access : read-only

OVERRUN : Over Run Flag (Read Only)\nIf converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after ADDR register is read.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

VALID : Valid Flag \nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.\nThis is a read only bit
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ADEN : A/D Converter Enable\nBefore starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADIE : A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMD : A/D Converter Operation Mode When changing the operation mode, software should disable ADST bit firstly. Note: In Burst Mode, the A/D result data always at Data Register 0.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGS : Hardware Trigger Source\nSoftware should disable TRGEN and ADST before change TRGS. \nIn hardware trigger mode, the ADST bit is set by the external trigger from STADC.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGCOND : External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.\n
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGEN : External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin.\nADC external trigger function is only supported in single-cycle scan mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIFFEN : Differential Input Mode Enable\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADST : A/D Conversion Start\nADST bit can be set to 1 from two sources: software and external pin STADC. ADST will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan and burst modes, A/D conversion is continuously performed until software write 0 to this bit or chip reset.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN0 : Analog Input Channel 0 Enable\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN1 : Analog Input Channel 1 Enable\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN2 : Analog Input Channel 2 Enable\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN3 : Analog Input Channel 3 Enable\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN4 : Analog Input Channel 4 Enable\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN5 : Analog Input Channel 5 Enable\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN6 : Analog Input Channel 6 Enable\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN7 : Analog Input Channel 7 Enable\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRESEL : Analog Input Channel 7 select\nNote:\nWhen software select the band-gap voltage as the analog input source of ADC channel 7, ADC clock rate needs to be limited to lower than 300 KHz.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPEN : Compare Enable\nSet this bit to 1 to enable ADC controller to compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADDR register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPIE : Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCOND : Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCH : Compare Channel Selection\n
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPMATCNT : Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
bits : 8 - 11 (4 bit)
access : read-write

CMPD : Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel.
bits : 16 - 27 (12 bit)
access : read-write

ADF : A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these three conditions:\nWhen A/D conversion ends in single mode\nWhen A/D conversion ends on all specified channels in scan mode.\nWhen more than 4 samples in FIFO in Burst mode.\nThis flag can be cleared by writing 1 to self.
bits : 0 - 0 (1 bit)
access : read-write

CMPF0 : Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPF1 : Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSY : BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.\nIt is read only.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHANNEL : Current Conversion Channel\nIt is read only.
bits : 4 - 6 (3 bit)
access : read-write

VALID : Data Valid flag (Read Only)\nIt is a mirror of VALID bit in ADDRx\nWhen ADC in Burst Mode, and the FIFO is valid, VALID[7:0] will all set to 1.
bits : 8 - 15 (8 bit)
access : read-only

OVERRUN : Over Run flag (Read Only)\nIt is a mirror to OVERRUN bit in ADDRx\nWhen ADC in Burst Mode, and the FIFO is overrun, OVERRUN[7:0] will all set to 1.
bits : 16 - 23 (8 bit)
access : read-only

CALEN : Self Calibration Enable\nSoftware can set this bit to 1 enables A/D converter to do self calibration function. It needs 127 ADC clocks to complete calibration. This bit must be kept at 1 after CALDONE asserted. Clearing this bit will disable self calibration function.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CALDONE : Calibration is Done (read only)\nWhen 0 is written to CALEN bit, CALDONE bit is cleared by hardware immediately. It is a read only bit.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.