\n

EBI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

EBICON

EXTIME


EBICON

External Bus Interface General Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EBICON EBICON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ExtEN ExtBW16 MCLKDIV ExttALE

ExtEN : EBI Enable\nThis bit is the functional enable bit for EBI.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

EBI function is disabled

#1 : 1

EBI function is enabled

End of enumeration elements list.

ExtBW16 : EBI data width 16 bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

EBI data width is 8 bit

#1 : 1

EBI data width is 16 bit

End of enumeration elements list.

MCLKDIV : External Output Clock Divider\n
bits : 8 - 10 (3 bit)
access : read-write

ExttALE : Expand Time of ALE\nThe ALE width (tALE) to latch the address can be controlled by ExttALE.\n
bits : 16 - 18 (3 bit)
access : read-write


EXTIME

External Bus Interface Timing Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTIME EXTIME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ExttACC ExttAHD ExtIW2X ExtIR2R

ExttACC : EBI Data Access Time\nExttACC define data access time (tACC).\n
bits : 3 - 7 (5 bit)
access : read-write

ExttAHD : EBI Data Access Hold Time\nExttAHD define data access hold time (tAHD).\n
bits : 8 - 10 (3 bit)
access : read-write

ExtIW2X : Idle State Cycle After Write\nWhen write action is finish, idle state is inserted and nCS return to high if ExtIW2X is not zero.\n
bits : 12 - 15 (4 bit)
access : read-write

ExtIR2R : Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read, idle state is inserted and nCS return to high if ExtIR2R is not zero.\n
bits : 24 - 27 (4 bit)
access : read-write



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