\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
CPUID Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REVISION : Revision Number\nRead as 0x0.
bits : 0 - 3 (4 bit)
access : read-only
PARTNO : Part Number of the Processor\nRead as 0xC20.
bits : 4 - 15 (12 bit)
access : read-only
PART : Architecture of the Processor\nRead as 0xC for ARMv6-M parts.
bits : 16 - 19 (4 bit)
access : read-only
IMPLEMENTER : Implementer Code\n
bits : 24 - 31 (8 bit)
access : read-only
System Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : Sleep-on-exit Enable Control\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not sleep when returning to Thread mode
#1 : 1
Enter Sleep or Deep Sleep when returning from ISR to Thread mode
End of enumeration elements list.
SLEEPDEEP : Processor Deep Sleep and Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode:\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sleep mode
#1 : 1
Deep Sleep mode
End of enumeration elements list.
SEVONPEND : Send Event on Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded
#1 : 1
Enabled events and all interrupts, including disabled interrupts, can wake-up the processor
End of enumeration elements list.
System Handler Priority Register 2
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_11 : Priority of System Handler 11 - SVCall
0 denotes the highest priority and 3 denotes the lowest priority
bits : 30 - 31 (2 bit)
access : read-write
System Handler Priority Register 3
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_14 : Priority of System Handler 14 - PendSV
0 denotes the highest priority and 3 denotes the lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_15 : Priority of System Handler 15 - SysTick
0 denotes the highest priority and 3 denotes the lowest priority
bits : 30 - 31 (2 bit)
access : read-write
Interrupt Control State Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTACTIVE : Contains the Active Exception Number\n
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Thread mode
End of enumeration elements list.
VECTPENDING : Exception Number of the Highest Priority Pending Enabled Exception\n
bits : 12 - 17 (6 bit)
access : read-write
Enumeration:
0 : 0
No pending exceptions
End of enumeration elements list.
ISRPENDING : Interrupt Pending Flag, Excluding NMI and Faults (Read Only)\n
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not pending
#1 : 1
Interrupt pending
End of enumeration elements list.
ISRPREEMPT : Interrupt Preempt Bit\nIf set, a pending exception will be serviced on exit from the debug halt state.\nThis bit is read only.
bits : 23 - 23 (1 bit)
access : read-write
PENDSTCLR : SysTick Exception Clear-pending Bit
Write:
Note: This bit is write-only. When you want to clear PENDST bit, you must write 0 to PENDSTSET and write 1 to PENDSTCLR at the same time.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Removes the pending state from the SysTick exception
End of enumeration elements list.
PENDSTSET : SysTick Exception Set-pending Bit\nWrite:\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nSysTick exception is not pending
#1 : 1
Changes SysTick exception state to pending.\nSysTick exception is pending
End of enumeration elements list.
PENDSVCLR : PendSV Clear-pending Bit
Write:
This bit is write-only. To clear the PENDSV bit, you must write 0 to PENDSVSET and write 1 to PENDSVCLR at the same time.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Removes the pending state from the PendSV exception
End of enumeration elements list.
PENDSVSET : PendSV Set-pending Bit\nWrite:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nPendSV exception is not pending
#1 : 1
Changes PendSV exception state to pending.\nPendSV exception is pending
End of enumeration elements list.
NMIPENDSET : NMI Set-pending Bit\nWrite:\nNote: Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNMI exception not pending
#1 : 1
Changes NMI exception state to pending.\nNMI exception pending
End of enumeration elements list.
Application Interrupt and Reset Control Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTCLRACTIVE : Exception Active Status Clear Bit\nReserved for debug use. When writing to the register, user must write 0 to this bit, otherwise behavior is unpredictable.
bits : 1 - 1 (1 bit)
access : read-write
SYSRESETREQ : System Reset Request\nWriting this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence.
bits : 2 - 2 (1 bit)
access : read-write
VECTORKEY : Register Access Key\nWrite:\nWhen writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.\nRead:\nRead as 0xFA05.
bits : 16 - 31 (16 bit)
access : read-write
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