\n

CLK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PWRCON

CLKSEL0

CLKSEL1

CLKDIV

CLKSEL2

PLLCON

FRQDIV

AHBCLK

APBCLK

CLKSTATUS


PWRCON

System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWRCON PWRCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTL12M_EN OSC22M_EN OSC10K_EN PD_WU_DLY PD_WU_INT_EN PD_WU_STS PWR_DOWN_EN PD_WAIT_CPU

XTL12M_EN : 4~24 MHz External High Speed Crystal (HXT) Enable Control (Write Protect)\nThe bit default value is set by flash controller user configuration register config0 [26:24]. When the default clock source is from 4~24 MHz external high speed crystal, this bit is set to 1 automatically.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

4 ~ 24 MHz external high speed crystal oscillator (HXT) Disabled

#1 : 1

4 ~ 24 MHz external high speed crystal oscillator (HXT) Enabled

End of enumeration elements list.

OSC22M_EN : 22.1184 MHz Internal High Speed RC Oscillator (HIRC) Enable Control (Write Protect)\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

22.1184 MHz internal high speed RC oscillator (HIRC) Disabled

#1 : 1

22.1184 MHz internal high speed RC oscillator (HIRC) Enabled

End of enumeration elements list.

OSC10K_EN : 10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Control (Write Protect)\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

10 kHz internal low speed RC oscillator (LIRC) Disabled

#1 : 1

10 kHz internal low speed RC oscillator (LIRC) Enabled

End of enumeration elements list.

PD_WU_DLY : Wake-up Delay Counter Enable Control (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal (HXT), and 256 clock cycles when chip works at 22.1184 MHz internal high speed RC oscillator (HIRC).\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock cycles delay Disabled

#1 : 1

Clock cycles delay Enabled

End of enumeration elements list.

PD_WU_INT_EN : Power-down Mode Wake-up Interrupt Enable Control (Write Protect) Note: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

PD_WU_STS : Power-down Mode Wake-up Interrupt Status Set by Power-down wake-up event , which indicates that resume from Power-down mode The flag is set if the GPIO, UART, WDT, ACMP or BOD wake-up occurred. Note: This bit works only if PD_WU_INT_EN (PWRCON[5]) set to 1. Write 1 to clear the bit to 0.
bits : 6 - 6 (1 bit)
access : read-write

PWR_DOWN_EN : System Power-down Enable Bit (Write Protect)\nWhen this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depend on the PD_WAIT_CPU bit\n(a) If the PD_WAIT_CPU is 0, then the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set.\n(b) If the PD_WAIT_CPU is 1, then the chip keeps active till CPU run WFI instruction.\nWhen chip wakes up from Power-down mode, this bit is cleared by hardware. User needs to set this bit again for next Power-down.\nIn Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT) and the 22.1184 MHz internal high speed oscillator (HIRC) will be disabled in this mode, and 10 kHz internal low speed RC oscillator (LIRC) are not controlled by Power-down mode.\nIn Power- down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from 10 kHz internal low speed oscillator.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip operating normally or chip in Idle mode because of WFI command

#1 : 1

Chip enters Power-down mode instantly or waits CPU sleep command WFI

End of enumeration elements list.

PD_WAIT_CPU : Power-down Entry Condition Control (Write Protect)\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1

#1 : 1

Chip enters Power- down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction

End of enumeration elements list.


CLKSEL0

Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSEL0 CLKSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLK_S STCLK_S

HCLK_S : HCLK Clock Source Selection (Write Protect) Note1: Before clock switching, the related clock sources (both pre-select and new-select) must be turn-on and stable. Note2: The 3-bit default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b. Note3: These bits are protected bit, and programming them needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source is from HXT

#001 : 1

Reserved

#010 : 2

Clock source is from PLL

#011 : 3

Clock source is from LIRC

#111 : 7

Clock source is from HIRC

End of enumeration elements list.

STCLK_S : Cortex-M0 SysTick Clock Source Selection From Reference Clock (Write Protect)\n
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source is from HXT

#001 : 1

Reserved

#010 : 2

Clock source is from HXT/2

#011 : 3

Clock source is from HCLK/2

#111 : 7

Clock source is from HIRC/2

End of enumeration elements list.


CLKSEL1

Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSEL1 CLKSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_S ADC_S SPI0_S SPI1_S TMR0_S TMR1_S TMR2_S TMR3_S UART_S PWM01_S PWM23_S

WDT_S : Watchdog Timer Clock Source Selection (Write Protect) Note: These bits are protected bits, and programming them needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Reserved

#01 : 1

Reserved

#10 : 2

Clock source is from HCLK/2048 clock

#11 : 3

Clock source is from LIRC

End of enumeration elements list.

ADC_S : ADC Peripheral Clock Source Selection\n
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source is from HXT

#01 : 1

Clock source is from PLL

#10 : 2

Clock source is from HCLK

#11 : 3

Clock source is from HIRC

End of enumeration elements list.

SPI0_S : SPI0 Clock Source Selection (M051xxDN/DE Only)\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source is from PLL

#1 : 1

Clock source is from HCLK

End of enumeration elements list.

SPI1_S : SPI1 Clock Source Selection (M051xxDN/DE Only)\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source is from PLL

#1 : 1

Clock source is from HCLK

End of enumeration elements list.

TMR0_S : TIMER0 Clock Source Selection\n
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source is from HXT

#010 : 2

Clock source is from HCLK

#011 : 3

Clock source is from external trigger T0. (M051xxDN/DE Only)

#101 : 5

Clock source is from LIRC. (M051xxDN/DE Only)

#111 : 7

Clock source is from HIRC

End of enumeration elements list.

TMR1_S : TIMER1 Clock Source Selection\n
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source is from HXT

#010 : 2

Clock source is from HCLK

#011 : 3

Clock source is from external trigger T1. (M051xxDN/DE Only)

#101 : 5

Clock source is from LIRC. (M051xxDN/DE Only)

#111 : 7

Clock source is from HIRC

End of enumeration elements list.

TMR2_S : TIMER2 Clock Source Selection\n
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source is from HXT

#010 : 2

Clock source is from HCLK

#011 : 3

Clock source is from external trigger T2. (M051xxDN/DE Only)

#101 : 5

Clock source is from LIRC. (M051xxDN/DE Only)

#111 : 7

Clock source is from HIRC

End of enumeration elements list.

TMR3_S : TIMER3 Clock Source Selection\n
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source is from HXT

#010 : 2

Clock source is from HCLK

#011 : 3

Clock source is from external trigger T3. (M051xxDN/DE Only)

#101 : 5

Clock source is from LIRC. (M051xxDN/DE Only)

#111 : 7

Clock source is from HIRC

End of enumeration elements list.

UART_S : UART Clock Source Selection\n
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source is from HXT

#01 : 1

Clock source is from PLL

#10 : 2

Reserved

#11 : 3

Clock source is from HIRC

End of enumeration elements list.

PWM01_S : PWM0 and PWM1 Clock Source Selection PWM0 and PWM1 use the same peripheral clock source both of them use the same prescaler.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source is from HXT

#01 : 1

Clock source is from LIRC. (M051xxDN/DE Only)

#10 : 2

Clock source is from HCLK

#11 : 3

Clock source is from HIRC

End of enumeration elements list.

PWM23_S : PWM2 and PWM3 Clock Source Selection PWM2 and PWM3 use the same peripheral clock source both of them use the same prescaler.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source is from HXT

#01 : 1

Clock source is from LIRC. (M051xxDN/DE Only)

#10 : 2

Clock source is from HCLK

#11 : 3

Clock source is from HIRC

End of enumeration elements list.


CLKDIV

Clock Divider Number Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKDIV CLKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLK_N UART_N ADC_N

HCLK_N : HCLK Clock Divide Number From HCLK Clock Source\n
bits : 0 - 3 (4 bit)
access : read-write

UART_N : UART Clock Divide Number From UART Clock Source\n
bits : 8 - 11 (4 bit)
access : read-write

ADC_N : ADC Peripheral Clock Divide Number From ADC Peripheral Clock Source\n
bits : 16 - 23 (8 bit)
access : read-write


CLKSEL2

Clock Source Select Control Register 2
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSEL2 CLKSEL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRQDIV_S PWM45_S PWM67_S WWDT_S

FRQDIV_S : Clock Divider Clock Source Selection\n
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source is from HXT

#01 : 1

Clock source is from LIRC. (M051xxDE Only)

#10 : 2

Clock source is from HCLK

#11 : 3

Clock source is from HIRC

End of enumeration elements list.

PWM45_S : PWM4 and PWM5 Clock Source Selection PWM4 and PWM5 use the same peripheral clock source both of them used the same prescaler.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source is from HXT

#01 : 1

Clock source is from LIRC. (M051xxDN/DE Only)

#10 : 2

Clock source is from HCLK

#11 : 3

Clock source is from HIRC

End of enumeration elements list.

PWM67_S : PWM6 and PWM7 Clock Source Selection PWM6 and PWM7 used the same peripheral clock source both of them used the same prescaler.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source is from HXT

#01 : 1

Clock source is from LIRC. (M051xxDN/DE Only)

#10 : 2

Clock source is from HCLK

#11 : 3

Clock source is from HIRC

End of enumeration elements list.

WWDT_S : Window Watchdog Timer Clock Source Selection (M051xxDN/DE Only)\n
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#10 : 2

Clock source is from HCLK/2048 clock

#11 : 3

Clock source is from LIRC

End of enumeration elements list.


PLLCON

PLL Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLLCON PLLCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FB_DV IN_DV OUT_DV PD BP OE PLL_SRC

FB_DV : PLL Feedback Divider Control\nRefer to the formulas below the table.
bits : 0 - 8 (9 bit)
access : read-write

IN_DV : PLL Input Divider Control\nRefer to the formulas below the table.
bits : 9 - 13 (5 bit)
access : read-write

OUT_DV : PLL Output Divider Control\nRefer to the formulas below the table.
bits : 14 - 15 (2 bit)
access : read-write

PD : Power-down Mode\nIf the PWR_DOWN_EN bit is set to 1 in PWRCON register, the PLL will enter Power-down mode too.\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in Normal mode

#1 : 1

PLL is in Power-down mode (default)

End of enumeration elements list.

BP : PLL Bypass Control\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in Normal mode (default)

#1 : 1

PLL clock output is same as PLL source clock input

End of enumeration elements list.

OE : PLL OE (FOUT Enable) Pin Control\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL FOUT Enabled

#1 : 1

PLL FOUT is fixed low

End of enumeration elements list.

PLL_SRC : PLL Source Clock Selection\n
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL source clock from HXT

#1 : 1

PLL source clock from HIRC

End of enumeration elements list.


FRQDIV

Frequency Divider Control Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRQDIV FRQDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSEL DIVIDER_EN DIVIDER1

FSEL : Divider Output Frequency Selection\nThe formula of output frequency is:\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write

DIVIDER_EN : Frequency Divider Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Frequency Divider Disabled

#1 : 1

Frequency Divider Enabled

End of enumeration elements list.

DIVIDER1 : Frequency Divider 1 Enable Control (M051xxDE Only) \n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Divider output frequency is depended on FSEL value

#1 : 1

Divider output frequency is the same as input clock frequency

End of enumeration elements list.


AHBCLK

AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBCLK AHBCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISP_EN EBI_EN HDIV_EN

ISP_EN : Flash ISP Controller Clock Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Flash ISP peripheral clock Disabled

#1 : 1

Flash ISP peripheral clock Enabled

End of enumeration elements list.

EBI_EN : EBI Controller Clock Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

EBI peripheral clock Disabled

#1 : 1

EBI peripheral clock Enabled

End of enumeration elements list.

HDIV_EN : Divider Controller Clock Enable Control (M05xxDN/DE Only)\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Divider controller peripheral clock Disabled

#1 : 1

Divider controller peripheral clock Enabled

End of enumeration elements list.


APBCLK

APB Devices Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APBCLK APBCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_EN TMR0_EN TMR1_EN TMR2_EN TMR3_EN FDIV_EN I2C0_EN I2C1_EN SPI0_EN SPI1_EN UART0_EN UART1_EN PWM01_EN PWM23_EN PWM45_EN PWM67_EN ADC_EN ACMP01_EN ACMP23_EN

WDT_EN : Watchdog Timer Clock Enable Control (Write Protect) Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog Timer clock Disabled

#1 : 1

Watchdog Timer clock Enabled

End of enumeration elements list.

TMR0_EN : Timer0 Clock Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer0 clock Disabled

#1 : 1

Timer0 clock Enabled

End of enumeration elements list.

TMR1_EN : Timer1 Clock Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer1 clock Disabled

#1 : 1

Timer1 clock Enabled

End of enumeration elements list.

TMR2_EN : Timer2 Clock Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer2 clock Disabled

#1 : 1

Timer2 clock Enabled

End of enumeration elements list.

TMR3_EN : Timer3 Clock Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer3 clock Disabled

#1 : 1

Timer3 clock Enabled

End of enumeration elements list.

FDIV_EN : Frequency Divider Output Clock Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

FDIV clock Disabled

#1 : 1

FDIV clock Enabled

End of enumeration elements list.

I2C0_EN : I2C0 Clock Enable Control\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C clock Disabled

#1 : 1

I2C clock Enabled

End of enumeration elements list.

I2C1_EN : I2C1 Clock Enable Control (M051xxDN/DE Only)\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C clock Disabled

#1 : 1

I2C clock Enabled

End of enumeration elements list.

SPI0_EN : SPI0 Peripheral Clock Enable Control\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI0 peripheral clock Disabled

#1 : 1

SPI0 peripheral clock Enabled

End of enumeration elements list.

SPI1_EN : SPI1 Peripheral Clock Enable Control\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI1 peripheral clock Disabled

#1 : 1

SPI1 peripheral clock Enabled

End of enumeration elements list.

UART0_EN : UART0 Clock Enable Control\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 clock Disabled

#1 : 1

UART0 clock Enabled

End of enumeration elements list.

UART1_EN : UART1 Clock Enable Control\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART1 clock Disabled

#1 : 1

UART1 clock Enabled

End of enumeration elements list.

PWM01_EN : PWM_01 Clock Enable Control\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM01 clock Disabled

#1 : 1

PWM01 clock Enabled

End of enumeration elements list.

PWM23_EN : PWM_23 Clock Enable Control\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM23 clock Disabled

#1 : 1

PWM23 clock Enabled

End of enumeration elements list.

PWM45_EN : PWM_45 Clock Enable Control\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM45 clock Disabled

#1 : 1

PWM45 clock Enabled

End of enumeration elements list.

PWM67_EN : PWM_67 Clock Enable Control\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM67 clock Disabled

#1 : 1

PWM67 clock Enabled

End of enumeration elements list.

ADC_EN : Analog-digital-converter (ADC) Clock Enable Control\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADC peripheral clock Disabled

#1 : 1

ADC peripheral clock Enabled

End of enumeration elements list.

ACMP01_EN : Analog Comparator 0/1 Clock Enable Control\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Analog Comparator 0/1 clock Disabled

#1 : 1

Analog Comparator 0/1 clock Enabled

End of enumeration elements list.

ACMP23_EN : Analog Comparator 2/3 Clock Enable Control (M051xxDN/DE Only)\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Analog Comparator 2/3 clock Disabled

#1 : 1

Analog Comparator 2/3 clock Enabled

End of enumeration elements list.


CLKSTATUS

Clock Status Monitor Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSTATUS CLKSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTL12M_STB PLL_STB OSC10K_STB OSC22M_STB CLK_SW_FAIL

XTL12M_STB : 4~24 MHz External High Speed Crystal (HXT) Stable Flag (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

4~24 MHz external high speed crystal (HXT) clock is not stable or disabled

#1 : 1

4~24 MHz external high speed crystal (HXT) clock is stable

End of enumeration elements list.

PLL_STB : Internal PLL Clock Source Stable Flag (Read Only)\n
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Internal PLL clock is not stable or disabled

#1 : 1

Internal PLL clock is stable

End of enumeration elements list.

OSC10K_STB : 10 KHz Internal Low Speed RC Oscillator (LIRC) Stable Flag (Read Only)\n
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled

#1 : 1

10 kHz internal low speed RC oscillator (LIRC) clock is stable

End of enumeration elements list.

OSC22M_STB : 22.1184 MHz Internal High Speed RC Oscillator (HIRC) Stable Flag (Read Only)\n
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

22.1184 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled

#1 : 1

22.1184 MHz internal high speed RC oscillator (HIRC) clock is stable

End of enumeration elements list.

CLK_SW_FAIL : Clock Switching Fail Flag\nNote1: This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote2: On M05xxBN, software can write 1 to clear the bit to 0.\nNote3: On M05xxDN/DE, this bit is read only. After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLK_SE_FAIL will be cleared automatically by hardware.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock switching success

#1 : 1

Clock switching failed

End of enumeration elements list.



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