PPR

CMR0

PDR0

CNR1

CMR1

PDR1

CNR2

CMR2

PDR2

CNR3

CMR3

PDR3

CSR

PIER

PIIR

CCR0

CCR2

CRLR0

CFLR0

CRLR1

CFLR1

CRLR2

CFLR2

CRLR3

CFLR3

CAPENR

POE

PCR

TCON

TSTATUS

PSCR

CNR0

CP01 : Clock Prescaler 0 (PWM-timer 0 / 1 for Group A and PWM-timer 4 / 5 for Group B)\nClock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-Timer\n
bits : 0 - 7 (8 bit)
access : read-write

CP23 : Clock Prescaler 2 (PWM-timer 2 / 3 for Group A and PWM-timer 6 / 7 for Group B)\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-Timer.\n
bits : 8 - 15 (8 bit)
access : read-write

DZI01 : Dead-zone Interval for Pair of Channel 0 and Channel 1 (PWM0 and PWM1 Pair for PWM Group A, PWM4 and PWM5 Pair for PWM Group B)\nThese 8-bit determine the Dead-zone length.\n
bits : 16 - 23 (8 bit)
access : read-write

DZI23 : Dead-zone Interval for Pair of Channel 2 and Channel 3 (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B)\nThese 8-bit determine the Dead-zone length.\n
bits : 24 - 31 (8 bit)
access : read-write

CMRx : PWM Comparator Register\nCMR determines the PWM duty.\nNote: Any write operation to CMR will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

PDRx : PWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter.
bits : 0 - 15 (16 bit)
access : read-only

CSR0 : PWM Timer 0 Clock Source Divider Selection (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nSelect clock source divider for PWM timer 0.\n(Table is the same as CSR3)
bits : 0 - 2 (3 bit)
access : read-write

CSR1 : PWM Timer 1 Clock Source Divider Selection (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nSelect clock source divider for PWM timer 1.\n(Table is the same as CSR3)
bits : 4 - 6 (3 bit)
access : read-write

CSR2 : PWM Timer 2 Clock Source Divider Selection (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nSelect clock source divider for PWM timer 2.\n(Table is the same as CSR3)
bits : 8 - 10 (3 bit)
access : read-write

CSR3 : PWM Timer 3 Clock Source Divider Selection (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n
bits : 12 - 14 (3 bit)
access : read-write

PWMIE0 : PWM Channel 0 Period Interrupt Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMIE1 : PWM Channel 1 Period Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMIE2 : PWM Channel 2 Period Interrupt Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMIE3 : PWM Channel 3 Period Interrupt Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMDIE0 : PWM Channel 0 Duty Interrupt Enable Control (M05xxDN/DE Only)\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMDIE1 : PWM Channel 1 Duty Interrupt Enable Control (M05xxDN/DE Only)\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMDIE2 : PWM Channel 2 Duty Interrupt Enable Control (M05xxDN/DE Only)\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMDIE3 : PWM Channel 3 Duty Interrupt Enable Control (M05xxDN/DE Only)\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INT01TYPE : PWM01 Interrupt Period Type Selection (PWM0 and PWM1 Pair for PWM Group A, PWM4 and PWM5 Pair for PWM Group B) (M05xxDN/DE Only)\nNote: Setting INT01TYPE to 1 only works when PWM operating is in center-aligned type.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INT23TYPE : PWM23 Interrupt Period Type Selection (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B) (M05xxDN/DE Only)\nNote: Setting INT23TYPE to 1 only works when PWM operating is in center-aligned type.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INT01DTYPE : PWM01 Duty Interrupt Type Selection (PWM0 and PWM1 Pair for PWM Group A, PWM4 and PWM5 Pair for PWM Group B) (M05xxDN/DE Only)\nNote: Set INT01DTYPE to 1 only work when PWM operating in center aligned type.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INT23DTYPE : PWM23 Duty Interrupt Type Selection (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B) (M05xxDN/DE Only)\nNote: Set INT23DTYPE to 1 only work when PWM operating in center aligned type.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMIF0 : PWM Channel 0 Period Interrupt Status\nOn M05xxBN:\nThis bit is set by hardware when channel 0 PWM counter equal to zero if channel 0 PWM period interrupt enable bit (PWMIE0) is 1. Software can write 1 to clear this bit to 0.\nOn M05xxDN/DE:\nNote: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

PWMIF1 : PWM Channel 1 Period Interrupt Status\nOn M05xxBN:\nThis bit is set by hardware when channel 1 PWM counter equal to zero if channel 1 PWM period interrupt enable bit (PWMIE1) is 1. Software can write 1 to clear this bit to 0.\nOn M05xxDN/DE:\nNote: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

PWMIF2 : PWM Channel 2 Period Interrupt Status\nOn M05xxBN:\nThis bit is set by hardware when channel 2 PWM counter equal to zero if channel 2 PWM period interrupt enable bit (PWMIE2) is 1. Software can write 1 to clear this bit to 0.\nOn M05xxDN/DE:\nNote: Write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write

PWMIF3 : PWM Channel 3 Period Interrupt Status\nOn M05xxBN:\nThis bit is set by hardware when channel 3 PWM counter equal to zero if channel 3 PWM period interrupt enable bit (PWMIE3) is 1. Software can write 1 to clear this bit to 0.\nOn M05xxDN/DE:\nNote: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

PWMDIF0 : PWM Channel 0 Duty Interrupt Status (M05xxDN/DE Only)\nNote: Write 1 to clear this bit to 0.
bits : 8 - 8 (1 bit)
access : read-write

PWMDIF1 : PWM Channel 1 Duty Interrupt Status (M05xxDN/DE Only)\nNote: Write 1 to clear this bit to 0.
bits : 9 - 9 (1 bit)
access : read-write

PWMDIF2 : PWM Channel 2 Duty Interrupt Status (M05xxDN/DE Only)\nNote: Write 1 to clear this bit to 0.
bits : 10 - 10 (1 bit)
access : read-write

PWMDIF3 : PWM Channel 3 Duty Interrupt Status (M05xxDN/DE Only)\nNote: Write 1 to clear this bit to 0.
bits : 11 - 11 (1 bit)
access : read-write

INV0 : Capture Channel 0 Inverter Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE0 : Channel 0 Rising Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 0 has rising transition, Capture will issue an Interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE0 : Channel 0 Falling Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 0 has falling transition, and Capture will issue an Interrupt.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH0EN : Channel 0 Capture Function Enable Control\nNote1: When Enabled, Capture latches the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 0 Interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF0 : Channel 0 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

CRLRI0 : CRLR0 Latched Indicator When PWM group input channel 0 has a rising transition, CRLR0 was latched with the value of PWM down-counter and this bit is set by hardware. Note: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write

CFLRI0 : CFLR0 Latched Indicator Control\nWhen PWM group input channel 0 has a falling transition, CFLR0 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

INV1 : Capture Channel 1 Inverter Enable Control\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE1 : Channel 1 Rising Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 1 has rising transition, Capture will issue an Interrupt.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE1 : Channel 1 Falling Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 1 has falling transition, Capture will issue an Interrupt.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH1EN : Channel 1 Capture Function Enable Control\nNote1: When Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 1 Interrupt.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF1 : Channel 1 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0.
bits : 20 - 20 (1 bit)
access : read-write

CRLRI1 : CRLR1 Latched Indicator \nWhen PWM group input channel 1 has a rising transition, CRLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0.
bits : 22 - 22 (1 bit)
access : read-write

CFLRI1 : CFLR1 Latched Indicator\nWhen PWM group input channel 1 has a falling transition, CFLR1 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0.
bits : 23 - 23 (1 bit)
access : read-write

INV2 : Capture Channel 2 Inverter Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE2 : Channel 2 Rising Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 2 has rising transition, Capture will issue an Interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE2 : Channel 2 Falling Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 2 has falling transition, Capture will issue an Interrupt.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH2EN : Channel 2 Capture Function Enable Control\nNote1: When Enabled, Capture latched the PWM-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 2 Interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF2 : Channel 2 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

CRLRI2 : CRLR2 Latched Indicator\nWhen PWM group input channel 2 has a rising transition, CRLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write

CFLRI2 : CFLR2 Latched Indicator\nWhen PWM group input channel 2 has a falling transition, CFLR2 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

INV3 : Capture Channel 3 Inverter Enable Control\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE3 : Channel 3 Rising Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 3 has rising transition, Capture will issue an Interrupt.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE3 : Channel 3 Falling Latch Interrupt Enable Control\nNote: When Enabled, if Capture detects PWM group channel 3 has falling transition, Capture will issue an Interrupt.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH3EN : Channel 3 Capture Function Enable Control\nNote1: When Enabled, Capture latched the PWM-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nNote2: When Disabled, Capture does not update CRLR and CFLR, and disable PWM group channel 3 Interrupt.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF3 : Channel 3 Capture Interrupt Indication Flag\nNote: Write 1 to clear this bit to 0.
bits : 20 - 20 (1 bit)
access : read-write

CRLRI3 : CRLR3 Latched Indicator \nWhen PWM group input channel 3 has a rising transition, CRLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0.
bits : 22 - 22 (1 bit)
access : read-write

CFLRI3 : CFLR3 Latched Indicator\nWhen PWM group input channel 3 has a falling transition, CFLR3 was latched with the value of PWM down-counter and this bit is set by hardware.\nNote: Write 1 to clear this bit to 0.
bits : 23 - 23 (1 bit)
access : read-write

CRLRx : Capture Rising Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has rising transition.
bits : 0 - 15 (16 bit)
access : read-only

CFLRx : Capture Falling Latch Register\nLatch the PWM counter value when Channel 0/1/2/3 has Falling transition.
bits : 0 - 15 (16 bit)
access : read-only

CAPENR : Capture Input Enable Register CAPENR Bit 3210 for PWM group A Bit xxx1 ( Capture channel 0 enabled. Capture input channel can be from P2.0 or P4.0. User can only select one of pins by setting multi-function pin register. Bit xx1x ( Capture channel 1 enabled. Capture input channel can be from P2.1 or P4.1. User can only select one of pins by setting multi-function pin register. Bit x1xx ( Capture channel 2 enabled. Capture input channel can be from P2.2 or P4.2. User can only select one of pins by setting multi-function pin register. Bit 1xxx ( Capture channel 3 enabled. Capture input channel can be from P2.3 or P4.3. User can only select one of pins by setting multi-function pin register. Bit 3210 for PWM group B Bit xxx1 ( Capture channel 0 enabled. Capture input channel can be from P2.4 by setting multi-function pin register. Bit xx1x ( Capture channel 1 enabled. Capture input channel can be from P2.5 by setting multi-function pin register. Bit x1xx ( Capture channel 2 enabled. Capture input channel can be from P2.6 by setting multi-function pin register. Bit 1xxx ( Capture channel 3 enabled. Capture input channel can be from P2.7 by setting multi-function pin register.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0 : Channel 0 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1 : Channel 1 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM2 : Channel 2 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM3 : Channel 3 Output Enable Register\nNote: The corresponding GPIO pin must also be switched to PWM function.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0EN : PWM-timer 0 Enable Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0PINV : PWM-timer 0 Output Polar Inverse Enable Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B) (M05xxDN/DE Only)\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0INV : PWM-timer 0 Output Inverter Enable Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0MOD : PWM-timer 0 Auto-reload/One-shot Mode Control (PWM Timer 0 for Group A and PWM Timer 4 for Group B)\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be cleared.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DZEN01 : Dead-zone 0 Generator Enable Control (PWM0 and PWM1 Pair for PWM Group A, PWM4 and PWM5 Pair for PWM Group B)\nNote: When Dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group A and the pair of PWM4 and PWM5 becomes a complementary pair for PWM group B.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DZEN23 : Dead-zone 2 Generator Enable (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B)\nNote: When Dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group A and the pair of PWM6 and PWM7 becomes a complementary pair for PWM group B.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1EN : PWM-timer 1 Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1PINV : PWM-timer 1 Output Polar Inverse Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B) (M05xxDN/DE Only)\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1INV : PWM-timer 1 Output Inverter Enable (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1MOD : PWM-timer 1 Auto-reload/One-shot Mode (PWM Timer 1 for Group A and PWM Timer 5 for Group B)\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be cleared.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2EN : PWM-timer 2 Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2PINV : PWM-timer 2 Output Polar Inverse Enable (PWM Timer 2 for Group A and PWM Timer 6 for Group B) (M05xxDN/DE Only)\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2INV : PWM-timer 2 Output Inverter Enable Control (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2MOD : PWM-timer 2 Auto-reload/One-shot Mode Control (PWM Timer 2 for Group A and PWM Timer 6 for Group B)\nNote: If there is a transition at this bit, it will cause CNR2 and CMR2 be cleared.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH3EN : PWM-timer 3 Enable Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH3PINV : PWM-timer 3 Output Polar Inverse Enable Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B) (M05xxDN/DE Only)\n
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH3INV : PWM-timer 3 Output Inverter Enable Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH3MOD : PWM-timer 3 Auto-reload/One-shot Mode Control (PWM Timer 3 for Group A and PWM Timer 7 for Group B)\nNote: If there is a transition at this bit, it will cause CNR3 and CMR3 be cleared.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM01TYPE : PWM01 Aligned Type Selection Bit (PWM0 and PWM1 Pair for PWM Group A, PWM4 and PWM5 Pair for PWM Group B) (M05xxDN/DE Only)\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM23TYPE : PWM23 Aligned Type Selection Bit (PWM2 and PWM3 Pair for PWM Group A, PWM6 and PWM7 Pair for PWM Group B) (M05xxDN/DE Only)\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0TEN : Channel 0 PWM Period Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 0 counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 0 counter up count to (CNR0 + 1) or down count to underflow based on INT01PTYPE setting.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1TEN : Channel 1 PWM Period Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 1 counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 1 counter up count to (CNR1 + 1) or down count to underflow based on INT01PTYPE setting.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM2TEN : Channel 2 PWM Period Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 2 counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 2 counter up count to (CNR2 + 1) or down count to underflow based on INT23PTYPE setting.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM3TEN : Channel 3 PWM Period Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 3 counter down count to underflow.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 3 counter up count to (CNR3 + 1) or down count to underflow based on INT23PTYPE setting.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0DTEN : Channel 0 PWM Duty Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 0 counter down count to match CMR0.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 0 counter up count or down count to match CMR0 based on INT01DTYPE setting.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1DTEN : Channel 1 PWM Duty Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 1 counter down count to match CMR1.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 1 counter up count or down count to match CMR1 based on INT01DTYPE setting.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM2DTEN : Channel 2 PWM Duty Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 2 counter down count to match CMR2.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 2 counter up count or down count to match CMR2 based on INT23DTYPE setting.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM3DTEN : Channel 3 PWM Duty Trigger ADC Enable Control (M05xxDN/DE Only)\nAs PWM operating at edge-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 3 counter down count to match CMR3.\nAs PWM operating at center-aligned type, enable this bit can make PWM trigger ADC to start conversion when PWM channel 3 counter up count or down count to match CMR3 based on INT23DTYPE setting.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0TF : Channel 0 PWM Trigger ADC Flag (M05xxDN/DE Only)\nThis bit is set to 1 by hardware when PWM channel 0 trigger ADC condition matched. ADC will start conversion if ADC triggered source is selected by PWM while this bit is set to 1.\nNote: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

PWM1TF : Channel 1 PWM Trigger ADC Flag (M05xxDN/DE Only)\nThis bit is set to 1 by hardware when PWM channel 1 trigger ADC condition matched. ADC will start conversion if ADC triggered source is selected by PWM while this bit is set to 1.\nNote: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

PWM2TF : Channel 2 PWM Trigger ADC Flag (M05xxDN/DE Only)\nThis bit is set to 1 by hardware when PWM channel 2 trigger ADC condition matched. ADC will start conversion if ADC triggered source is selected by PWM while this bit is set to 1.\nNote: Write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write

PWM3TF : Channel 3 PWM Trigger ADC Flag (M05xxDN/DE Only)\nThis bit is set to 1 by hardware when PWM channel 3 trigger ADC condition matched. ADC will start conversion if ADC triggered source is selected by PWM while this bit is set to 1.\nNote: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

PSSEN0 : Channel 0 PWM-timer Synchronous Start Enable Control (M05xxDN/DE Only)\nIf this bit is set to 1, the PWM-Timer channel 0 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in PWM group A.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PSSEN1 : Channel 1 PWM-timer Synchronous Start Enable Control (M05xxDN/DE Only)\nIf this bit is set to 1, the PWM-Timer channel 1 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in PWM group A.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PSSEN2 : Channel 2 PWM-timer Synchronous Start Enable Control (M05xxDN/DE Only)\nIf this bit is set to 1, the PWM-Timer channel 2 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in PWM group A.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PSSEN3 : Channel 3 PWM-timer Synchronous Start Enable Control (M05xxDN/DE Only)\nIf this bit is set to 1, the PWM-Timer channel 3 of specified PWM group will synchronously start with PWM-Timer channel 0 of PWM group A when SW writes 1 to CH0EN(PCR[0]) in PWM group A.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNRx : PWM Timer Loaded Value\nCNR determines the PWM period.\nNote1: Any write operation to CNR will take effect in next PWM cycle.\nNote2: When CNR value is set to 0, PWM output is always high.\nNote3: When PWM operating at center-aligned type, CNR value should be set between 0x0001 to 0xFFFE. If CNR equal to 0x0000 or 0xFFFF, the PWM will work unpredictable.
bits : 0 - 15 (16 bit)
access : read-write