\n
address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GO_BUSY : SPI Transfer Trigger and Busy Status\nOn M05xxBN:\nDuring the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNote 1: When FIFO mode is disabled, all configurations should be ready before writing 1 to the GO_BUSY bit.\nNote 2: In M05xxDN/DE SPI Slave mode, if FIFO mode is disabled and the SPI bus clock is kept at idle state during a data transfer, the GO_BUSY bit will not be cleared to 0 when slave select signal goes to inactive state.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit to stop data transfer if SPI is transferring
#1 : 1
In Master mode, writing 1 to this bit will start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master.
In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
End of enumeration elements list.
RX_NEG : Receive on Negative Edge\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The received data input signal is latched on the rising edge of SPICLK
#1 : 1
The received data input signal is latched on the falling edge of SPICLK
End of enumeration elements list.
TX_NEG : Transmit on Negative Edge\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transmitted data output signal is driven on the rising edge of SPICLK
#1 : 1
The transmitted data output signal is driven on the falling edge of SPICLK
End of enumeration elements list.
TX_BIT_LEN : Transfer Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
bits : 3 - 7 (5 bit)
access : read-write
TX_NUM : Numbers of Transmit/Receive Word (M05xxBN Only)\nThis field specifies how many transmit/receive word numbers should be executed in one transfer.\nNote: In Slave mode with level-trigger configuration, if TX_NUM is set to 01, the slave\nselect pin must be kept at active state during the successive data transfer.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Burst mode Disabled. Only one word will be transferred when the GO_BUSY bit is set to 1
#01 : 1
Burst mode Enabled. Two successive words will be transferred when the GO_BUSY bit is set to 1
#10 : 2
Reserved
#11 : 3
Reserved
End of enumeration elements list.
LSB : LSB First\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB is transmitted/received first
#1 : 1
The LSB is transmitted/received first
End of enumeration elements list.
CLKP : Clock Polarity\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPICLK idle low
#1 : 1
SPICLK idle high
End of enumeration elements list.
SP_CYCLE : Suspend Interval (Master Only)\nThese four bits provide configurable suspend interval between two successive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.\nOn M05xxBN:\n
bits : 12 - 15 (4 bit)
access : read-write
IF : Unit-transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No transaction has been finished since this bit was cleared to 0
#1 : 1
SPI controller has finished one unit transfer
End of enumeration elements list.
IE : Unit-transfer Interrupt Enable Control\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI unit-transfer interrupt Disabled
#1 : 1
SPI unit-transfer interrupt Enabled
End of enumeration elements list.
SLAVE : Slave Mode Control\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
REORDER : Byte Reorder Function and Byte Suspend Function Selection\nOn M05xxBN:\nNote: Byte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#00 : 0
Disable both byte reorder and byte suspend functions.\nByte reorder function and byte suspend function are Disabled
#01 : 1
Enable byte reorder function and insert a byte suspend interval (2~17 SPICLK cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00 (32 bits).\nByte reorder function Enabled. Byte suspend interval is determined by the setting of SP_CYCLE. Set SP_CYCLE to 0 to disabled byte suspend function
#10 : 2
Enable byte reorder function, but disable byte suspend function.\nReserved
#11 : 3
Disable byte reorder function, but insert a suspend interval (2~17 SPICLK cycles) among each byte. The setting of TX_BIT_LEN must be configured as 0x00 (32 bits).\nReserved
End of enumeration elements list.
FIFO : FIFO Mode Enable Control (M05xxDN/DE Only)\nIn Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data into the 8-depth transmit FIFO. When all data stored at transmit FIFO buffer are transferred, the GO_BUSY bit will back to 0.\nNote 1: Before enabling FIFO mode, the other related settings should be set in advance.\nNote 2: On M05xxBN, this bit must be 0.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Mode Disabled
#1 : 1
FIFO Mode Enabled
End of enumeration elements list.
VARCLK_EN : Variable Clock Enable Control (M05xxBN Master Mode Only)\nNote: When this VARCLK_EN bit is set, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode).
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bus clock output frequency is fixed and decided only by the value of DIVIDER
#1 : 1
The bus clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2
End of enumeration elements list.
RX_EMPTY : Receive FIFO Buffer Empty Indicator (Read Only) (M05xxDN/DE Only)\nIt is a mutual mirror bit of SPI_CNTRL[24]. \n
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates that the receive FIFO buffer is not empty
#1 : 1
Indicates that the receive FIFO buffer is empty
End of enumeration elements list.
RX_FULL : Receive FIFO Buffer Full Indicator (Read Only) (M05xxDN/DE Only)\nIt is a mutual mirror bit of SPI_STATUS[25].\n
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates that the receive FIOF buffer is not full
#1 : 1
Indicates that the receive FIFO buffer is full
End of enumeration elements list.
TX_EMPTY : Transmit FIFO Buffer Empty Indicator (Read Only) (M05xxDN/DE Only)\nIt is a mutual mirror bit of SPI_STATUS[26]. \n
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates that the transmit FIFO buffer is not empty
#1 : 1
Indicates that the transmit FIFO buffer is empty
End of enumeration elements list.
TX_FULL : Transmit FIFO Buffer Full Indicator (Read Only) (M05xxDN/DE Only)\nIt is a mutual mirror bit of SPI_STATUS[27]. \n
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates that the transmit FIFO buffer is not full
#1 : 1
Indicates that the transmit FIFO buffer is full
End of enumeration elements list.
Data Receive Register 0
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. The values of the other bits are unknown. The Data Receive Registers are read-only registers.
bits : 0 - 31 (32 bit)
access : read-only
Data Receive Register 1 (M05xxBN Only)
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Transmit Register 0
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the SPI controller will perform two 32-bit transmit/receive successive using the same setting. The transmission sequence is TX0[31:0] first and then TX1[31:0].
bits : 0 - 31 (32 bit)
access : write-only
Data Transmit Register 1 (M05xxBN Only)
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Variable Clock Pattern Register (M05xxBN Only)
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VARCLK : Variable Clock Pattern\nThe value in this field is the frequency patterns of the SPI bus clock. If the bit pattern of VARCLK is '0', the output frequency of SPICLK is according the value of DIVIDER. If the bit patterns of VARCLK are '1', the output frequency of SPICLK is according the value of DIVIDER2. Refer to the SPI_DIVIDER register.\nNote: Refer to the Variable Bus Clock Frequency paragraph for more detailed description.
bits : 0 - 31 (32 bit)
access : read-write
Control and Status Register 2
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIV_ONE : SPI Bus Clock Divider Control (M05xxBN Master Mode Only)\nNote: When this bit is set to 1, both the REORDER field and the VARCLK_EN field must be configured as 0. In other words, the byte-reorder function, byte suspend function and variable clock function must be disabled.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The SPI bus clock rate is determined by the setting of SPI_DIVIDER register
#1 : 1
Enable the DIV_ONE feature. The SPI bus clock rate equals the system clock rate
End of enumeration elements list.
NOSLVSEL : Slave 3-wire Mode Enable\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI when this bit is set to 1.\nNote: In Slave 3-wire mode, the SS_LTRIG bit (SPI_SSR[4]) shall be set as 1.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The controller is 4-wire bi-direction interface
#1 : 1
The controller is 3-wire bi-direction interface in Slave mode. When this bit is set to 1, the controller will be ready to transmit/receive data after the GO_BUSY bit is set to 1
End of enumeration elements list.
SLV_ABORT : Slave 3-wire Mode Abort Control\nIn normal operation, there is an interrupt event when the number of received bits meets the requirement which defined in TX_BIT_LEN and TX_NUM. The TX_NUM setting is not available on M05xxDN/DE, and only the setting of TX_BIT_LEN will be considered.\nIf the number of received bits is less than the requirement and there is no more bus clock input over one transfer time in Slave 3-wire mode, user can set this bit to force the current transfer done and then user can get a unit transfer interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
bits : 9 - 9 (1 bit)
access : read-write
SSTA_INTEN : Slave 3-wire Mode Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, user can set the SLV_ABORT bit to force the transfer done.\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transaction start interrupt Disabled
#1 : 1
Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared to 0
End of enumeration elements list.
SLV_START_INTSTS : Slave 3-wire Mode Start Interrupt Status\nThis bit dedicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave does not detect any SPI bus clock transition since the SSTA_INTEN bit was set to 1
#1 : 1
A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit
End of enumeration elements list.
SS_INT_OPT : Slave Select Inactive Interrupt Option (M05xxDN/DE Only)\nThis setting is only available if the SPI controller is configured as level trigger slave device.\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#1 : 1
As the slave select signal goes to inactive level, the IF bit will be set to 1
End of enumeration elements list.
BCn : Clock Configuration Backward Compatible Option (M05xxDN/DE Only)\nRefer to the description of SPI_DIVIDER register for details.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The clock configuration is backward compatible to M05xxBN
#1 : 1
The clock configuration is not backward compatible to M05xxBN
End of enumeration elements list.
Clock Divider Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER : Clock Divider\nOn M05xxBN:\nOnly available in Master mode. The value in this field is the frequency divider to determine the master's peripheral clock frequency and the bus clock frequency on the SPICLK output pin. The desired frequency is obtained according to the following equation:\n\nIn Slave mode, the period of SPI bus clock driven by a master shall equal or over 5 times the period of PCLK. In other words, the maximum frequency of SPI bus clock is the fifth of the frequency of slave's PCLK.\n\nOn M05xxDN/DE:\nOnly DIVIDER[7:0] is available. The value in this field is the frequency divider to determine the SPI peripheral clock frequency, fspi, and the SPI master's bus clock frequency on the SPICLK output pin. The frequency is obtained according to the following equation.\nIf the bit of BCn, SPI_CNTRL2[31], is set to 0,\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI peripheral clock source which is defined in the CLKSEL1 register.
bits : 0 - 15 (16 bit)
access : read-write
DIVIDER2 : Clock Divider 2 (M05xxBN Master Mode Only)\nThe value in this field is the 2nd frequency divider for generating the bus clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIf VARCLK_EN is cleared to 0, this setting is unmeaning.
bits : 16 - 31 (16 bit)
access : read-write
SPI FIFO Control Register (M05xxDN/DE Only)
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CLR : Clear Receive FIFO Buffer\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1 and the receive FIFO is cleared
End of enumeration elements list.
TX_CLR : Clear Transmit FIFO Buffer\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1 and the transmit FIFO is cleared
End of enumeration elements list.
RX_INTEN : Receive Threshold Interrupt Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive threshold interrupt Disabled
#1 : 1
Receive threshold interrupt Enabled
End of enumeration elements list.
TX_INTEN : Transmit Threshold Interrupt Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit threshold interrupt Disabled
#1 : 1
Transmit threshold interrupt Enabled
End of enumeration elements list.
RXOV_INTEN : Receive FIFO Overrun Interrupt Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO overrun interrupt Disabled
#1 : 1
Receive FIFO overrun interrupt Enabled
End of enumeration elements list.
TIMEOUT_INTEN : Receive FIFO Time-out Interrupt Enable Control\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time-out interrupt Disabled
#1 : 1
Time-out interrupt Enabled
End of enumeration elements list.
RX_THRESHOLD : Received FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
bits : 24 - 25 (2 bit)
access : read-write
TX_THRESHOLD : Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
bits : 28 - 29 (2 bit)
access : read-write
SPI Status Register (M05xxDN/DE Only)
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_INTSTS : Receive FIFO Threshold Interrupt Status (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#1 : 1
The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
End of enumeration elements list.
RX_OVERRUN : Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
bits : 2 - 2 (1 bit)
access : read-write
TX_INTSTS : Transmit FIFO Threshold Interrupt Status (Read Only)\n
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#1 : 1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
End of enumeration elements list.
SLV_START_INTSTS : Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in Slave 3-wire mode. It's a mutual mirror bit of SPI_CNTRL2[11].\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transfer is not started
#1 : 1
The transfer has started in Slave 3-wire mode. It will be cleared as transfer done or by writing one to this bit
End of enumeration elements list.
RX_FIFO_COUNT : Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer.
bits : 12 - 15 (4 bit)
access : read-only
IF : SPI Unit-transfer Interrupt Flag\nIt is a mutual mirror bit of SPI_CNTRL[16]. \nNote: This bit will be cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transfer does not finish yet
#1 : 1
The SPI controller has finished one unit transfer
End of enumeration elements list.
TIMEOUT : Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No receive FIFO time-out event
#1 : 1
The receive FIFO buffer is not empty and it does not be read over 64 SPI clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
End of enumeration elements list.
RX_EMPTY : Receive FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[24]. \n
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
The receive FIFO buffer is not empty
#1 : 1
The receive FIFO buffer is empty
End of enumeration elements list.
RX_FULL : Receive FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[25]. \n
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
The receive FIFO buffer is not full
#1 : 1
The receive FIFO buffer is full
End of enumeration elements list.
TX_EMPTY : Transmit FIFO Buffer Empty Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[26]. \n
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
The transmit FIFO buffer is not empty
#1 : 1
The transmit FIFO buffer is empty
End of enumeration elements list.
TX_FULL : Transmit FIFO Buffer Full Indicator (Read Only)\nIt is a mutual mirror bit of SPI_CNTRL[27].\n
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
The transmit FIFO buffer is not full
#1 : 1
The transmit FIFO buffer is full
End of enumeration elements list.
TX_FIFO_COUNT : Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer.
bits : 28 - 31 (4 bit)
access : read-only
Slave Select Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSR : Slave Select Control (Master Only)\nIf AUTOSS bit is cleared to 0,\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the SPISSx line to inactive state.\nKeep the SPISSx line at inactive state
#1 : 1
Set the proper SPISSx line to active state.\nSelect the SPISSx line to be automatically driven to active state for the duration of transmission/reception, and will be driven to inactive state for the rest of the time. The active state of SPISSx is specified in SS_LVL bit
End of enumeration elements list.
SS_LVL : Slave Select Active Level\nThis bit defines the active status of slave select signal (SPISSx).\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The slave select signal SPISSx is active at low-level/falling-edge
#1 : 1
The slave select signal SPISSx is active at high-level/rising-edge
End of enumeration elements list.
AUTOSS : Automatic Slave Select Function Enable (Master Only)\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
If this bit is cleared, slave select signal will be asserted/de-asserted by setting /clearing SSR bit
#1 : 1
If this bit is set, SPISSx signal will be generated automatically, which means that slave select signal will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished
End of enumeration elements list.
SS_LTRIG : Slave Select Level Trigger Enable (Slave Only)\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The input slave select signal is edge-trigger. This is the default value. It depends on SS_LVL to decide the signal is active at falling-edge or rising-edge
#1 : 1
The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high
End of enumeration elements list.
LTRIG_FLAG : Level Trigger Flag\nWhen the SS_LTRIG bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not.\nNote: This bit is READ only and only available in Slave mode.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transaction number or the transferred bit length of one transaction does not meet the specified requirements
#1 : 1
The transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN. The TX_NUM setting is not available on M05xxDN/DE, only the setting of TX_BIT_LEN will be considered
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.