\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
Timer0 Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESCALE : Prescale Counter\n
bits : 0 - 7 (8 bit)
access : read-write
TDR_EN : Data Load Enable Control\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer Data Register update Disabled
#1 : 1
Timer Data Register update Enabled while Timer counter is active
End of enumeration elements list.
INTR_TRG_EN : Inter-timer Trigger Mode Enable Control (M05xxDN/DE Only)\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in counter mode and counting with external clock source or event.Also, Timer1/3 will be in trigger-counting mode of capture function.\nNote: For Timer1/3, this bit is ignored and the read back value is always 0.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inter-Timer Trigger Capture mode Disabled
#1 : 1
Inter-Timer Trigger Capture mode Enabled
End of enumeration elements list.
PERIODIC_SEL : Periodic Mode Behavior Selection Enable (M05xxDN/DE Only)
If updated TCMP value TDR, TDR will be reset to default value.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
The behavior selection in periodic mode is Disabled
#1 : 1
The behavior selection in periodic mode is Enabled
End of enumeration elements list.
TOUT_SEL : Toggle-output Pin Selection (M05xxDN/DE Only)\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Toggle-output pin is from Tx pin
#1 : 1
Toggle-output pin is from TxEx pin
End of enumeration elements list.
CAP_SRC : Capture Pin Source Selection (M05xxDN/DE Only)\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture Function source is from TxEX pin
#1 : 1
Capture Function source is from internal ACMPx output signal
End of enumeration elements list.
WAKE_EN : Wake-up Function Enable Control (M05xxDN/DE Only)\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up trigger event Disabled
#1 : 1
Wake-up trigger event Enabled
End of enumeration elements list.
CTB : Counter Mode Enable Control\nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 6.7.5.3 for detail description.\n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
External event counter mode Disabled
#1 : 1
External event counter mode Enabled
End of enumeration elements list.
CACT : Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
24-bit up counter is not active
#1 : 1
24-bit up counter is active
End of enumeration elements list.
CRST : Timer Reset\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset 8-bit prescale counter, 24-bit up counter value and CEN bit if CACT is 1
End of enumeration elements list.
MODE : Timer Operating Mode\n
bits : 27 - 28 (2 bit)
access : read-write
Enumeration:
#00 : 0
The Timer controller is operated in One-shot mode
#01 : 1
The Timer controller is operated in Periodic mode
#10 : 2
The Timer controller is operated in Toggle-output mode
#11 : 3
The Timer controller is operated in Continuous Counting mode
End of enumeration elements list.
IE : Interrupt Enable Control\nIf this bit is enabled, when the timer interrupt flag (TIF) is set to 1, the timer interrupt signal is generated and inform to CPU.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer Interrupt function Disabled
#1 : 1
Timer Interrupt function Enabled
End of enumeration elements list.
CEN : Timer Enable Control\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stops/Suspends counting
#1 : 1
Starts counting
End of enumeration elements list.
DBGACK_TMR : ICE Debug Mode Acknowledge Disable (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement effects TIMER counting
#1 : 1
ICE debug mode acknowledgement Disabled
End of enumeration elements list.
Timer0 Capture Data Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TCAP : Timer Capture Data Register\nWhen TEXIF flag is set to 1, the current TDR value will be auto-loaded into this TCAP filed immediately.
bits : 0 - 23 (24 bit)
access : read-only
Timer0 External Control Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_PHASE : Timer External Count Pin Phase Detect Selection\nThis bit indicates the detection phase of Tx pin.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
A falling edge of Tx pin will be counted
#1 : 1
A rising edge of Tx pin will be counted
End of enumeration elements list.
TEX_EDGE : Timer External Capture Pin Edge Detect Selection\n
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 0
A 1 to 0 transition on TxEX pin will be detected
#01 : 1
A 0 to 1 transition on TxEX pin will be detected
#10 : 2
Either 1 to 0 or 0 to 1 transition on TxEX pin will be detected
#11 : 3
Reserved
End of enumeration elements list.
TEXEN : Timer External Pin Function Enable\nThis bit enables the RSTCAPSEL function on the TxEX pin.\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
RSTCAPSEL function of TxEX pin will be ignored
#1 : 1
RSTCAPSEL function of TxEX pin is active
End of enumeration elements list.
RSTCAPSEL : Timer External Reset Counter / Timer External Capture Mode Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transition on TxEX pin is using to save the TDR value into TCAP value if TEXIF flag is set to 1
#1 : 1
Transition on TxEX pin is using to reset the 24-bit up counter
End of enumeration elements list.
TEXIEN : Timer External Capture Interrupt Enable Control\nIf TEXIEN enabled, Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
TxEX pin detection Interrupt Disabled
#1 : 1
TxEX pin detection Interrupt Enabled
End of enumeration elements list.
TEXDB : Timer External Capture Input Pin De-bounce Enable Control\nIf this bit is enabled, the edge detection of TxEX pin is detected with de-bounce circuit.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
TxEX pin de-bounce Disabled
#1 : 1
TxEX pin de-bounce Enabled
End of enumeration elements list.
TCDB : Timer External Counter Input Pin De-bounce Enable Control\nIf this bit is enabled, the edge detection of Tx pin is detected with de-bounce circuit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx pin de-bounce Disabled
#1 : 1
Tx pin de-bounce Enabled
End of enumeration elements list.
Timer0 External Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEXIF : Timer External Capture Interrupt Flag\nThis bit indicates the external capture interrupt flag status.\nWhen TEXEN enabled, TxEX pin selected as external capture function, and a transition on TxEX pin matched the TEX_EDGE setting, this flag will set to 1 by hardware.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
TxEX pin interrupt did not occur
#1 : 1
TxEX pin interrupt occurred
End of enumeration elements list.
Timer1 Control and Status Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Compare Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Interrupt Status Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Data Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Capture Data Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 External Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 External Interrupt Status Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer0 Compare Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCMP : Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When Timer is operating at Continuous Counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into TCMP field. But if Timer is operating at other modes except Periodic mode on M05xxDN/DE, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if software writes a new value into TCMP field.
bits : 0 - 23 (24 bit)
access : read-write
Timer0 Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIF : Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
TDR value matches the TCMP value
End of enumeration elements list.
TWF : Timer Wake-up Flag (M05xxDN/DE Only)\nThis bit indicates the interrupt wake-up flag status of Time.\nNote: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer does not cause chip wake-up
#1 : 1
Chip wake-up from Idle or Power-down mode if Timer time-out interrupt signal generated
End of enumeration elements list.
Timer0 Data Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TDR : Timer Data Register\nIf TDR_EN is set to 1, TDR register value will be updated continuously to monitor 24-bit up counter value.
bits : 0 - 23 (24 bit)
access : read-only
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