GP

PIN0 : Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n
bits : 0 - 0 (1 bit)
access : read-only

PIN1 : Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n
bits : 1 - 1 (1 bit)
access : read-only

PIN2 : Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n
bits : 2 - 2 (1 bit)
access : read-only

PIN3 : Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n
bits : 3 - 3 (1 bit)
access : read-only

PIN4 : Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n
bits : 4 - 4 (1 bit)
access : read-only

PIN5 : Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n
bits : 5 - 5 (1 bit)
access : read-only

PIN6 : Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n
bits : 6 - 6 (1 bit)
access : read-only

PIN7 : Px Pin Values\nThe value read from each of these bit reflects the actual status of the respective Px pin\n
bits : 7 - 7 (1 bit)
access : read-only

P4_PMD

P4 Pin I/O Mode Control
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_OFFD

P4 Digital Input Path Disable Control
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_DOUT

P4 Data Output Value
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_DMASK

P4 Data Output Write Mask
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_PIN

P4 Pin Value
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_DBEN

P4 De-bounce Enable
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_IMD

P4 Interrupt Mode Control
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_IEN

P4 Interrupt Enable
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_ISRC

P4 Interrupt Source Flag
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_DBEN

P0 De-bounce Enable
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBEN0 : Px Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN1 : Px Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN2 : Px Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN3 : Px Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN4 : Px Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN5 : Px Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN6 : Px Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN7 : Px Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt Note: It is recommended setting this bit to '0' if GPIO is chosen as power down wakeup source. If set this bit to '1', will cause GPIO to produce interrupt twice. One is caused by wake up event, the other one is caused by delayed de-bounce result.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

P0_IMD

P0 Interrupt Mode Control
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMD0 : Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD1 : Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD2 : Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD3 : Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD4 : Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD5 : Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD6 : Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD7 : Port 0-7 Interrupt Mode Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

DBNCECON

De-bounce Cycle Control
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBCLKSEL : De-bounce sampling cycle selection\n
bits : 0 - 3 (4 bit)
access : read-write

DBCLKSRC : De-bounce counter clock source select\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

De-bounce counter clock source is the HCLK

#1 : 1

De-bounce counter clock source is the internal 10kHz clock

End of enumeration elements list.

ICLK_ON : Interru\nIt is recommended to turn off this bit to save system power, if on special application concern.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1

#1 : 1

All IO pins edge detection circuit is always active after reset

End of enumeration elements list.

P0_IEN

P0 Interrupt Enable
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF_EN0 : Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IF_EB[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Px[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the Px[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN1 : Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IF_EB[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Px[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the Px[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN2 : Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IF_EB[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Px[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the Px[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN3 : Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IF_EB[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Px[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the Px[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN4 : Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IF_EB[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Px[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the Px[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN5 : Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IF_EB[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Px[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the Px[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN6 : Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IF_EB[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Px[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the Px[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN7 : Port 0-7 Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IF_EB[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from high-to-low will generate the interrupt.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Px[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the Px[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IR_EN0 : Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IR_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Px[n] level-high or low-to-high interrupt

#1 : 1

Enable the Px[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN1 : Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IR_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Px[n] level-high or low-to-high interrupt

#1 : 1

Enable the Px[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN2 : Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IR_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Px[n] level-high or low-to-high interrupt

#1 : 1

Enable the Px[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN3 : Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IR_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Px[n] level-high or low-to-high interrupt

#1 : 1

Enable the Px[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN4 : Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IR_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Px[n] level-high or low-to-high interrupt

#1 : 1

Enable the Px[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN5 : Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IR_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Px[n] level-high or low-to-high interrupt

#1 : 1

Enable the Px[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN6 : Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IR_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Px[n] level-high or low-to-high interrupt

#1 : 1

Enable the Px[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN7 : Port 0-7 Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input Px[n]. Set bit 1 also enable the pin wakeup function When set the IR_EN[n] bit 1 : If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input Px[n] state change from low-to-high will generate the interrupt.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the Px[n] level-high or low-to-high interrupt

#1 : 1

Enable the Px[n] level-high or low-to-high interrupt

End of enumeration elements list.

P0_ISRC

P0 Interrupt Source Flag
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISRC0 : Port 0-7 Interrupt Source Flag Read :
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Px[n]\nNo action

#1 : 1

Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC1 : Port 0-7 Interrupt Source Flag Read :
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Px[n]\nNo action

#1 : 1

Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC2 : Port 0-7 Interrupt Source Flag Read :
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Px[n]\nNo action

#1 : 1

Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC3 : Port 0-7 Interrupt Source Flag Read :
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Px[n]\nNo action

#1 : 1

Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC4 : Port 0-7 Interrupt Source Flag Read :
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Px[n]\nNo action

#1 : 1

Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC5 : Port 0-7 Interrupt Source Flag Read :
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Px[n]\nNo action

#1 : 1

Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC6 : Port 0-7 Interrupt Source Flag Read :
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Px[n]\nNo action

#1 : 1

Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC7 : Port 0-7 Interrupt Source Flag Read :
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Px[n]\nNo action

#1 : 1

Indicates Px[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

P00_DOUT

P0.0 Data Output Value
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Pxn_PDIO : GPIO Px.n Pin Data Input/Output\nWrite this bit can control one GPIO pin output value\nRead this register to get GPIO pin status.\nFor example: write P00_PDIO will reflect the written value to bit P0_DOUT[0], read P00_PDIO will return the value of P0_PIN[0]\nNote: The write operation will not be affected by register Px_DMASK
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Set corresponding GPIO pin to low

#1 : 1

Set corresponding GPIO pin to high

End of enumeration elements list.

P01_DOUT

P0.1 Data Output Value
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P02_DOUT

P0.2 Data Output Value
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P03_DOUT

P0.3 Data Output Value
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P04_DOUT

P0.4 Data Output Value
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P05_DOUT

P0.5 Data Output Value
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P06_DOUT

P0.6 Data Output Value
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P07_DOUT

P0.7 Data Output Value
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P10_DOUT

P1.0 Data Output Value
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P11_DOUT

P1.1 Data Output Value
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P12_DOUT

P1.2 Data Output Value
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P13_DOUT

P1.3 Data Output Value
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P14_DOUT

P1.4 Data Output Value
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P15_DOUT

P1.5 Data Output Value
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P16_DOUT

P1.6 Data Output Value
address_offset : 0x238 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P17_DOUT

P1.7 Data Output Value
address_offset : 0x23C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P20_DOUT

P2.0 Data Output Value
address_offset : 0x240 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P21_DOUT

P2.1 Data Output Value
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P22_DOUT

P2.2 Data Output Value
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P23_DOUT

P2.3 Data Output Value
address_offset : 0x24C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P24_DOUT

P2.4 Data Output Value
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P25_DOUT

P2.5 Data Output Value
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P26_DOUT

P2.6 Data Output Value
address_offset : 0x258 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P27_DOUT

P2.7 Data Output Value
address_offset : 0x25C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P30_DOUT

P3.0 Data Output Value
address_offset : 0x260 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P31_DOUT

P3.1 Data Output Value
address_offset : 0x264 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P32_DOUT

P3.2 Data Output Value
address_offset : 0x268 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P33_DOUT

P3.3 Data Output Value
address_offset : 0x26C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P34_DOUT

P3.4 Data Output Value
address_offset : 0x270 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P35_DOUT

P3.5 Data Output Value
address_offset : 0x274 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P36_DOUT

P3.6 Data Output Value
address_offset : 0x278 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P37_DOUT

P3.7 Data Output Value
address_offset : 0x27C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P40_DOUT

P4.0 Data Output Value
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P41_DOUT

P4.1 Data Output Value
address_offset : 0x284 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P42_DOUT

P4.2 Data Output Value
address_offset : 0x288 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P43_DOUT

P4.3 Data Output Value
address_offset : 0x28C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P44_DOUT

P4.4 Data Output Value
address_offset : 0x290 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P45_DOUT

P4.5 Data Output Value
address_offset : 0x294 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P46_DOUT

P4.6 Data Output Value
address_offset : 0x298 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P47_DOUT

P4.7 Data Output Value
address_offset : 0x29C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_PMD

P5 Pin I/O Mode Control
address_offset : 0x2C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_OFFD

P5 Digital Input Path Disable Control
address_offset : 0x2C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_DOUT

P5 Data Output Value
address_offset : 0x2C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_DMASK

P5 Data Output Write Mask
address_offset : 0x2CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_PIN

P5 Pin Value
address_offset : 0x2D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_DBEN

P5 De-bounce Enable
address_offset : 0x2D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_IMD

P5 Interrupt Mode Control
address_offset : 0x2D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_IEN

P5 Interrupt Enable
address_offset : 0x2DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_ISRC

P5 Interrupt Source Flag
address_offset : 0x2E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P6_PMD

P6 Pin I/O Mode Control
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P6_OFFD

P6 Digital Input Path Disable Control
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P6_DOUT

P6 Data Output Value
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P6_DMASK

P6 Data Output Write Mask
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P6_PIN

P6 Pin Value
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P6_DBEN

P6 De-bounce Enable
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P6_IMD

P6 Interrupt Mode Control
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P6_IEN

P6 Interrupt Enable
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P6_ISRC

P6 Interrupt Source Flag
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P7_PMD

P7 Pin I/O Mode Control
address_offset : 0x340 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P7_OFFD

P7 Digital Input Path Disable Control
address_offset : 0x344 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P7_DOUT

P7 Data Output Value
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P7_DMASK

P7 Data Output Write Mask
address_offset : 0x34C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P7_PIN

P7 Pin Value
address_offset : 0x350 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P7_DBEN

P7 De-bounce Enable
address_offset : 0x354 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P7_IMD

P7 Interrupt Mode Control
address_offset : 0x358 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P7_IEN

P7 Interrupt Enable
address_offset : 0x35C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P7_ISRC

P7 Interrupt Source Flag
address_offset : 0x360 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P50_DOUT

P5.0 Data Output Value
address_offset : 0x380 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P51_DOUT

P5.1 Data Output Value
address_offset : 0x384 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P52_DOUT

P5.2 Data Output Value
address_offset : 0x388 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P53_DOUT

P5.3 Data Output Value
address_offset : 0x38C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P54_DOUT

P5.4 Data Output Value
address_offset : 0x390 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P55_DOUT

P5.5 Data Output Value
address_offset : 0x394 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P56_DOUT

P5.6 Data Output Value
address_offset : 0x398 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P57_DOUT

P5.7 Data Output Value
address_offset : 0x39C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P60_DOUT

P6.0 Data Output Value
address_offset : 0x3A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P61_DOUT

P6.1 Data Output Value
address_offset : 0x3A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P62_DOUT

P6.2 Data Output Value
address_offset : 0x3A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P63_DOUT

P6.3 Data Output Value
address_offset : 0x3AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P64_DOUT

P6.4 Data Output Value
address_offset : 0x3B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P65_DOUT

P6.5 Data Output Value
address_offset : 0x3B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P66_DOUT

P6.6 Data Output Value
address_offset : 0x3B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P67_DOUT

P6.7 Data Output Value
address_offset : 0x3BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P70_DOUT

P7.0 Data Output Value
address_offset : 0x3C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P71_DOUT

P7.1 Data Output Value
address_offset : 0x3C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_OFFD

P0 Digital Input Path Disable Control
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFD : OFFD: Px Pin[n] Digital Input Path Disable Control\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0 : 0

Enable IO digital input path

1 : 1

Disable IO digital input path (digital input tied to low)

End of enumeration elements list.

P1_PMD

P1 Pin I/O Mode Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_OFFD

P1 Digital Input Path Disable Control
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_DOUT

P1 Data Output Value
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_DMASK

P1 Data Output Write Mask
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_PIN

P1 Pin Value
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_DBEN

P1 De-bounce Enable
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_IMD

P1 Interrupt Mode Control
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_IEN

P1 Interrupt Enable
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_ISRC

P1 Interrupt Source Flag
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_DOUT

P0 Data Output Value
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOUT0 : Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px Pin[n] will drive Low if the corresponding output mode enabling bit is set

#1 : 1

Px Pin[n] will drive High if the corresponding output mode enabling bit is set

End of enumeration elements list.

DOUT1 : Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px Pin[n] will drive Low if the corresponding output mode enabling bit is set

#1 : 1

Px Pin[n] will drive High if the corresponding output mode enabling bit is set

End of enumeration elements list.

DOUT2 : Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px Pin[n] will drive Low if the corresponding output mode enabling bit is set

#1 : 1

Px Pin[n] will drive High if the corresponding output mode enabling bit is set

End of enumeration elements list.

DOUT3 : Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px Pin[n] will drive Low if the corresponding output mode enabling bit is set

#1 : 1

Px Pin[n] will drive High if the corresponding output mode enabling bit is set

End of enumeration elements list.

DOUT4 : Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px Pin[n] will drive Low if the corresponding output mode enabling bit is set

#1 : 1

Px Pin[n] will drive High if the corresponding output mode enabling bit is set

End of enumeration elements list.

DOUT5 : Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px Pin[n] will drive Low if the corresponding output mode enabling bit is set

#1 : 1

Px Pin[n] will drive High if the corresponding output mode enabling bit is set

End of enumeration elements list.

DOUT6 : Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px Pin[n] will drive Low if the corresponding output mode enabling bit is set

#1 : 1

Px Pin[n] will drive High if the corresponding output mode enabling bit is set

End of enumeration elements list.

DOUT7 : Px Pin[n] Output Value\nEach of these bits control the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px Pin[n] will drive Low if the corresponding output mode enabling bit is set

#1 : 1

Px Pin[n] will drive High if the corresponding output mode enabling bit is set

End of enumeration elements list.

P2_PMD

P2 Pin I/O Mode Control
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_OFFD

P2 Digital Input Path Disable Control
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_DOUT

P2 Data Output Value
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_DMASK

P2 Data Output Write Mask
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_PIN

P2 Pin Value
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_DBEN

P2 De-bounce Enable
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_IMD

P2 Interrupt Mode Control
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_IEN

P2 Interrupt Enable
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_ISRC

P2 Interrupt Source Flag
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_DMASK

P0 Data Output Write Mask
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMASK0 : Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding Px_DOUT[n] bit, and will not protect corresponding bit control register (P0x_DOUT, P1x_DOUT, P2x_DOUT, P3x_DOUT, P4x_DOUT, P5x_DOUT, P6x_DOUT, P7x_DOUT).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding Px_DOUT[n] bit can be updated

#1 : 1

The corresponding Px_DOUT[n] bit is protected

End of enumeration elements list.

DMASK1 : Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding Px_DOUT[n] bit, and will not protect corresponding bit control register (P0x_DOUT, P1x_DOUT, P2x_DOUT, P3x_DOUT, P4x_DOUT, P5x_DOUT, P6x_DOUT, P7x_DOUT).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding Px_DOUT[n] bit can be updated

#1 : 1

The corresponding Px_DOUT[n] bit is protected

End of enumeration elements list.

DMASK2 : Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding Px_DOUT[n] bit, and will not protect corresponding bit control register (P0x_DOUT, P1x_DOUT, P2x_DOUT, P3x_DOUT, P4x_DOUT, P5x_DOUT, P6x_DOUT, P7x_DOUT).
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding Px_DOUT[n] bit can be updated

#1 : 1

The corresponding Px_DOUT[n] bit is protected

End of enumeration elements list.

DMASK3 : Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding Px_DOUT[n] bit, and will not protect corresponding bit control register (P0x_DOUT, P1x_DOUT, P2x_DOUT, P3x_DOUT, P4x_DOUT, P5x_DOUT, P6x_DOUT, P7x_DOUT).
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding Px_DOUT[n] bit can be updated

#1 : 1

The corresponding Px_DOUT[n] bit is protected

End of enumeration elements list.

DMASK4 : Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding Px_DOUT[n] bit, and will not protect corresponding bit control register (P0x_DOUT, P1x_DOUT, P2x_DOUT, P3x_DOUT, P4x_DOUT, P5x_DOUT, P6x_DOUT, P7x_DOUT).
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding Px_DOUT[n] bit can be updated

#1 : 1

The corresponding Px_DOUT[n] bit is protected

End of enumeration elements list.

DMASK5 : Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding Px_DOUT[n] bit, and will not protect corresponding bit control register (P0x_DOUT, P1x_DOUT, P2x_DOUT, P3x_DOUT, P4x_DOUT, P5x_DOUT, P6x_DOUT, P7x_DOUT).
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding Px_DOUT[n] bit can be updated

#1 : 1

The corresponding Px_DOUT[n] bit is protected

End of enumeration elements list.

DMASK6 : Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding Px_DOUT[n] bit, and will not protect corresponding bit control register (P0x_DOUT, P1x_DOUT, P2x_DOUT, P3x_DOUT, P4x_DOUT, P5x_DOUT, P6x_DOUT, P7x_DOUT).
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding Px_DOUT[n] bit can be updated

#1 : 1

The corresponding Px_DOUT[n] bit is protected

End of enumeration elements list.

DMASK7 : Px Data Output Write Mask (write-protected)\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding Px_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding Px_DOUT[n] bit, and will not protect corresponding bit control register (P0x_DOUT, P1x_DOUT, P2x_DOUT, P3x_DOUT, P4x_DOUT, P5x_DOUT, P6x_DOUT, P7x_DOUT).
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding Px_DOUT[n] bit can be updated

#1 : 1

The corresponding Px_DOUT[n] bit is protected

End of enumeration elements list.

P3_PMD

P3 Pin I/O Mode Control
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_OFFD

P3 Digital Input Path Disable Control
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_DOUT

P3 Data Output Value
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_DMASK

P3 Data Output Write Mask
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_PIN

P3 Pin Value
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_DBEN

P3 De-bounce Enable
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_IMD

P3 Interrupt Mode Control
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_IEN

P3 Interrupt Enable
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_ISRC

P3 Interrupt Source Flag
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

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ChipSelect

GP

Peripheral Memory Blocks

Registers

P0_PMD

P0_PIN

P4_PMD

P4_OFFD

P4_DOUT

P4_DMASK

P4_PIN

P4_DBEN

P4_IMD

P4_IEN

P4_ISRC

P0_DBEN

P0_IMD

DBNCECON

P0_IEN

P0_ISRC

P00_DOUT

P01_DOUT

P02_DOUT

P03_DOUT

P04_DOUT

P05_DOUT

P06_DOUT

P07_DOUT

P10_DOUT

P11_DOUT

P12_DOUT

P13_DOUT

P14_DOUT

P15_DOUT

P16_DOUT

P17_DOUT

P20_DOUT

P21_DOUT

P22_DOUT

P23_DOUT

P24_DOUT

P25_DOUT

P26_DOUT

P27_DOUT

P30_DOUT

P31_DOUT

P32_DOUT

P33_DOUT

P34_DOUT

P35_DOUT

P36_DOUT

P37_DOUT

P40_DOUT

P41_DOUT

P42_DOUT

P43_DOUT

P44_DOUT

P45_DOUT

P46_DOUT

P47_DOUT

P5_PMD

P5_OFFD

P5_DOUT

P5_DMASK

P5_PIN

P5_DBEN

P5_IMD

P5_IEN

P5_ISRC

P6_PMD

P6_OFFD

P6_DOUT

P6_DMASK

P6_PIN

P6_DBEN

P6_IMD

P6_IEN

P6_ISRC

P7_PMD

P7_OFFD