ISPCON

ISPTRG

DFBADR

FATCON

ISPADR

ISPDAT

ISPCMD

ISPEN : ISP Enable (write-protected)\nISP function enable bit. Set this bit to enable ISP function.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BS : Boot Select (write-protected) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as MCU booting status flag, which can be used to check where MCU booted from. This bit is initiated with the inversed value of CBS in Config0 after power-on reset It keeps the same value at other reset.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

APUEN : APROM Update Enable (write-protected)\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGUEN : Config Update Enable (write-protected) Writing this bit to 1 enables s/w to update Configure value by ISP procedure regardless of program code is running in APROM or LDROM.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDUEN : LDROM Update Enable (write-protection bit)\nLDROM update enable bit.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (write-protection bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0\n(2) LDROM writes to itself if LDUEN is set to 0\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear.
bits : 6 - 6 (1 bit)
access : read-write

ISPGO : ISP start trigger(write-protected)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finish.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFBADR : Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nFor M058SLAN, the data flash size is 4KB and it start address is fixed at 0x0001_F000 by hardware internally.
bits : 0 - 31 (32 bit)
access : read-only

LFOM : Low Frequency Optimization Mode (Write-protection Bit)\nWhen chip operation frequency is lower than 25 MHz, chip can work more efficiently by setting this bit to 1\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPADR : ISP Address \nM058SLAN equips with a 8k x 32 embedded flash, it supports word program only. ISPADR[1:0] must be kept 2'b00 for ISP operation.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT : ISP Data Write data to this register before ISP program operation Read data from this register after ISP read operation
bits : 0 - 31 (32 bit)
access : read-write

FCTRL : ISP Command \n
bits : 0 - 3 (4 bit)
access : read-write

FCEN : ISP Command
bits : 4 - 4 (1 bit)
access : read-write

FOEN : ISP Command
bits : 5 - 5 (1 bit)
access : read-write