\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
CRYPTO_AES_FDBCK0 (AES_FDBCK0)
CRYPTO_AES_FDBCK1 (AES_FDBCK1)
CRYPTO_AES_FDBCK2 (AES_FDBCK2)
CRYPTO_AES_FDBCK3 (AES_FDBCK3)
CRYPTO_TDES_FDBCKH (TDES_FDBCKH)
CRYPTO_TDES_FDBCKL (TDES_FDBCKL)
Crypto Interrupt Enable Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AESIEN : AES Interrupt Enable Bit\nNote: In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine. In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
AES interrupt Disabled
#1 : 1
AES interrupt Enabled
End of enumeration elements list.
AESEIEN : AES Error Flag Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
AES error interrupt flag Disabled
#1 : 1
AES error interrupt flag Enabled
End of enumeration elements list.
TDESIEN : TDES/DES Interrupt Enable Bit\nNote: In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine. In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDES/DES interrupt Disabled
#1 : 1
TDES/DES interrupt Enabled
End of enumeration elements list.
TDESEIEN : TDES/DES Error Flag Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDES/DES error interrupt flag Disabled
#1 : 1
TDES/DES error interrupt flag Enabled
End of enumeration elements list.
PRNGIEN : PRNG Interrupt Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PRNG interrupt Disabled
#1 : 1
PRNG interrupt Enabled
End of enumeration elements list.
ECCIEN : ECC Interrupt Enable Bit\nNote: In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine. In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECC interrupt Disabled
#1 : 1
ECC interrupt Enabled
End of enumeration elements list.
ECCEIEN : ECC Error Interrupt Enable Bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECC error interrupt flag Disabled
#1 : 1
ECC error interrupt flag Enabled
End of enumeration elements list.
SHAIEN : SHA Interrupt Enable Bit\nNote: In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA engine. In Non-DMA mode, an interrupt will be triggered when the SHA engine finishes the operation.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
SHA interrupt Disabled
#1 : 1
SHA interrupt Enabled
End of enumeration elements list.
SHAEIEN : SHA Error Interrupt Enable Bit
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
SHA error interrupt flag Disabled
#1 : 1
SHA error interrupt flag Enabled
End of enumeration elements list.
PRNG Generated Key0
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG.
bits : 0 - 31 (32 bit)
access : read-only
PRNG Generated Key1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key2
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key3
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key4
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key5
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key6
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key7
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Crypto Interrupt Flag
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AESIF : AES Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AES interrupt
#1 : 1
AES encryption/decryption done interrupt
End of enumeration elements list.
AESEIF : AES Error Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AES error
#1 : 1
AES encryption/decryption error interrupt
End of enumeration elements list.
TDESIF : TDES/DES Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No TDES/DES interrupt
#1 : 1
TDES/DES encryption/decryption done interrupt
End of enumeration elements list.
TDESEIF : TDES/DES Error Flag\nThis bit includes the operating and setting error. The detailed flag is shown in the CRYPTO_TDES_STS register. This includes operating and setting error.\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No TDES/DES error
#1 : 1
TDES/DES encryption/decryption error interrupt
End of enumeration elements list.
PRNGIF : PRNG Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No PRNG interrupt
#1 : 1
PRNG key generation done interrupt
End of enumeration elements list.
ECCIF : ECC Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ECC interrupt
#1 : 1
ECC operation done interrupt
End of enumeration elements list.
ECCEIF : ECC Error Flag\nThis register includes operating and setting error. The detail flag is shown in CRYPTO_ECC_STS register.\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ECC error
#1 : 1
ECC error interrupt
End of enumeration elements list.
SHAIF : SHA Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No SHA interrupt
#1 : 1
SHA operation done interrupt
End of enumeration elements list.
SHAEIF : SHA Error Flag\nThis register includes operating and setting error. The detail flag is shown in CRYPTO_SHA_STS register.\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No SHA error
#1 : 1
SHA error interrupt
End of enumeration elements list.
AES Engine Output Feedback Data After Cryptographic Operation
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FDBCK : AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AESn_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for IV in the next block's operation. Software can use this feedback information to implement more than four DMA channels. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to CRYPTO_AESn_IVx in the same channel operation, and then continue the operation with the original setting.
bits : 0 - 31 (32 bit)
access : read-only
AES Engine Output Feedback Data After Cryptographic Operation
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Engine Output Feedback Data After Cryptographic Operation
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Engine Output Feedback Data After Cryptographic Operation
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Engine Output Feedback High Word Data After Cryptographic Operation
address_offset : 0x60 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FDBCK : TDES/DES Feedback\nThe feedback value is 64 bits in size.\nThe TDES/DES engine uses the data from {CRYPTO_TDES_FDBCKH, CRYPTO_TDES_FDBCKL} as the data inputted to {CRYPTO_TDESn_IVH, CRYPTO_TDESn_IVL} for the next block in DMA cascade mode. The feedback register is for CBC, CFB, and OFB mode.\nTDES/DES engine outputs feedback information for IV in the next block's operation. Software can use this feedback information to implement more than four DMA channels. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to CRYPTO_TDESn_IVH/L in the same channel operation. Then can continue the operation with the original setting.
bits : 0 - 31 (32 bit)
access : read-only
TDES/DES Engine Output Feedback Low Word Data After Cryptographic Operation
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Start PRNG Engine
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stop PRNG engine
#1 : 1
Generate new key and store the new key to register CRYPTO_PRNG_KEYx, which will be cleared when the new key is generated
End of enumeration elements list.
SEEDRLD : Reload New Seed for PRNG Engine
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Generating key based on the current seed
#1 : 1
Reload new seed
End of enumeration elements list.
KEYSZ : PRNG Generate Key Size
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
64 bits
#01 : 1
128 bits
#10 : 2
192 bits
#11 : 3
256 bits
End of enumeration elements list.
BUSY : PRNG Busy (Read Only)
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
PRNG engine is idle
#1 : 1
Indicate that the PRNG engine is generating CRYPTO_PRNG_KEYx
End of enumeration elements list.
Seed for PRNG
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SEED : Seed for PRNG (Write Only)\nThe bits store the seed for PRNG engine.
bits : 0 - 31 (32 bit)
access : write-only
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