\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
QEI Counter Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Quadrature Encoder Interface Counter \nA 32-bit up/down counter. When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF(QEI_STATUS[8]) is 0. This register performs an integrator which count value is proportional to the encoder position. The pulse counter may be initialized to a predetermined value by one of three events occurs:
bits : 0 - 31 (32 bit)
access : read-write
QEI Pre-set Maximum Count Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTMAX : Quadrature Encoder Interface Preset Maximum Count\nThis register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode.
bits : 0 - 31 (32 bit)
access : read-write
QEI Controller Control Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NFCLKSEL : Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock .
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
QEI_CLK
#001 : 1
QEI_CLK/2
#010 : 2
QEI_CLK/4
#011 : 3
QEI_CLK/16
#100 : 4
QEI_CLK/32
#101 : 5
QEI_CLK/64
End of enumeration elements list.
NFDIS : QEI Controller Input Noise Filter Disable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The noise filter of QEI controller Enabled
#1 : 1
The noise filter of QEI controller Disabled
End of enumeration elements list.
CHAEN : QEA Input to QEI Controller Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEA input to QEI Controller Disabled
#1 : 1
QEA input to QEI Controller Enabled
End of enumeration elements list.
CHBEN : QEB Input to QEI Controller Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEB input to QEI Controller Disabled
#1 : 1
QEB input to QEI Controller Enabled
End of enumeration elements list.
IDXEN : IDX Input to QEI Controller Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
IDX input to QEI Controller Disabled
#1 : 1
IDX input to QEI Controller Enabled
End of enumeration elements list.
MODE : QEI Counting Mode Selection\nThere are four quadrature encoder pulse counter operation modes.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
X4 Free-counting Mode
#01 : 1
X2 Free-counting Mode
#10 : 2
X4 Compare-counting Mode
#11 : 3
X2 Compare-counting Mode
End of enumeration elements list.
CHAINV : Inverse QEA Input Polarity
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not inverse QEA input polarity
#1 : 1
QEA input polarity is inversed to QEI controller
End of enumeration elements list.
CHBINV : Inverse QEB Input Polarity
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not inverse QEB input polarity
#1 : 1
QEB input polarity is inversed to QEI controller
End of enumeration elements list.
IDXINV : Inverse IDX Input Polarity
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not inverse IDX input polarity
#1 : 1
IDX input polarity is inversed to QEI controller
End of enumeration elements list.
OVUNIEN : OVUNF Trigger QEI Interrupt Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
OVUNF can trigger QEI controller interrupt Disabled
#1 : 1
OVUNF can trigger QEI controller interrupt Enabled
End of enumeration elements list.
DIRIEN : DIRCHGF Trigger QEI Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
DIRCHGF can trigger QEI controller interrupt Disabled
#1 : 1
DIRCHGF can trigger QEI controller interrupt Enabled
End of enumeration elements list.
CMPIEN : CMPF Trigger QEI Interrupt Enable Bit
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
CMPF can trigger QEI controller interrupt Disabled
#1 : 1
CMPF can trigger QEI controller interrupt Enabled
End of enumeration elements list.
IDXIEN : IDXF Trigger QEI Interrupt Enable Bit
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
The IDXF can trigger QEI interrupt Disabled
#1 : 1
The IDXF can trigger QEI interrupt Enabled
End of enumeration elements list.
HOLDTMR0 : Hold QEI_CNT by Timer 0
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT
#1 : 1
A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1
End of enumeration elements list.
HOLDTMR1 : Hold QEI_CNT by Timer 1
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT
#1 : 1
A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1
End of enumeration elements list.
HOLDTMR2 : Hold QEI_CNT by Timer 2
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT
#1 : 1
A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1
End of enumeration elements list.
HOLDTMR3 : Hold QEI_CNT by Timer 3
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT
#1 : 1
A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1
End of enumeration elements list.
HOLDCNT : Hold QEI_CNT Control
When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD(QEI_CNTHOLD[31:0]). This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]).
Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No operation
#1 : 1
QEI_CNT content is captured and stored in CNTHOLD(QEI_CNTHOLD[31:0])
End of enumeration elements list.
IDXLATEN : Index Latch QEI_CNT Enable Bit\nIf this bit is set to high, the CNT(QEI_CNT[31:0]) content will be latched into CNTLATCH (QEI_CNTLATCH[31:0]) at every rising on signal CHX.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
The index signal latch QEI counter function Disabled
#1 : 1
The index signal latch QEI counter function Enabled
End of enumeration elements list.
IDXRLDEN : Index Trigger QEI_CNT Reload Enable Bit
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reload function Disabled
#1 : 1
QEI_CNT re-initialized by Index signal Enabled
End of enumeration elements list.
CMPEN : The Compare Function Enable Bit\nThe compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function Disabled
#1 : 1
Compare function Enabled
End of enumeration elements list.
QEIEN : Quadrature Encoder Interface Controller Enable Bit
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEI controller function Disabled
#1 : 1
QEI controller function Enabled
End of enumeration elements list.
QEI Controller Status Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDXF : IDX Detected Flag\nWhen the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.\nNote: This bit is only cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No rising edge detected on signal CHX
#1 : 1
A rising edge occurs on signal CHX
End of enumeration elements list.
CMPF : Compare-match Flag\nIf the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]).\nNote: This bit is only cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0])
#1 : 1
QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0])
End of enumeration elements list.
OVUNF : QEI Counter Overflow or Underflow Flag\nFlag is set by hardware while CNT(QEI_CNT[31:0]) overflows from 0xFFFF_FFFF to 0 in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to 0 in compare-counting mode. Similarly, the flag is set while QEI counter underflows from 0 to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]).\nNote: This bit is only cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No overflow or underflow occurs in QEI counter
#1 : 1
QEI counter occurs counting overflow or underflow
End of enumeration elements list.
DIRCHGF : Direction Change Flag\nFlag is set by hardware while QEI counter counting direction is changed. Software can clear this bit by writing 1 to it.\nNote: This bit is only cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No change in QEI counter counting direction
#1 : 1
QEI counter counting direction is changed
End of enumeration elements list.
DIRF : QEI Counter Counting Direction Indication\nNote: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEI Counter is in down-counting
#1 : 1
QEI Counter is in up-counting
End of enumeration elements list.
QEI Counter Hold Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTHOLD : Quadrature Encoder Interface Counter Hold\nWhen the bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register.
bits : 0 - 31 (32 bit)
access : read-write
QEI Counter Index Latch Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTLATCH : Quadrature Encoder Interface Counter Index Latch\nWhen the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register.
bits : 0 - 31 (32 bit)
access : read-write
QEI Counter Compare Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTCMP : Quadrature Encoder Interface Counter Compare
bits : 0 - 31 (32 bit)
access : read-write
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