\n
address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
Input Capture Counter (24-bit Up Counter)
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from thme clock divider.
bits : 0 - 23 (24 bit)
access : read-write
Input Capture Compare Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTCMP : Input Capture Counter Compare Register
bits : 0 - 23 (24 bit)
access : read-write
Input Capture Control Register 0
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NFCLKSEL : Noise Filter Clock Pre-divide Selection\nTo determine the sampling frequency of the Noise Filter clock
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
CAP_CLK
#001 : 1
CAP_CLK/2
#010 : 2
CAP_CLK/4
#011 : 3
CAP_CLK/16
#100 : 4
CAP_CLK/32
#101 : 5
CAP_CLK/64
End of enumeration elements list.
CAPNFDIS : Input Capture Noise Filter Disable Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of Input Capture Enabled
#1 : 1
Noise filter of Input Capture Disabled (Bypass)
End of enumeration elements list.
IC0EN : Port Pin IC0 Input to Input Capture Unit Enable Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
IC0 input to Input Capture Unit Disabled
#1 : 1
IC0 input to Input Capture Unit Enabled
End of enumeration elements list.
IC1EN : Port Pin IC1 Input to Input Capture Unit Enable Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
IC1 input to Input Capture Unit Disabled
#1 : 1
IC1 input to Input Capture Unit Enabled
End of enumeration elements list.
IC2EN : Port Pin IC2 Input to Input Capture Unit Enable Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
IC2 input to Input Capture Unit Disabled
#1 : 1
IC2 input to Input Capture Unit Enabled
End of enumeration elements list.
CAPSEL0 : CAP0 Input Source Selection
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
CAP0 input is from port pin ICAP0
#01 : 1
Reserved.
#10 : 2
CAP0 input is from signal CHA of QEI controller unit n
#11 : 3
Reserved.
End of enumeration elements list.
CAPSEL1 : CAP1 Input Source Selection
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
CAP1 input is from port pin ICAP1
#01 : 1
Reserved.
#10 : 2
CAP1 input is from signal CHB of QEI controller unit n
#11 : 3
Reserved.
End of enumeration elements list.
CAPSEL2 : CAP2 Input Source Selection
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
CAP2 input is from port pin ICAP2
#01 : 1
Reserved.
#10 : 2
CAP2 input is from signal CHX of QEI controller unit n
#11 : 3
Reserved.
End of enumeration elements list.
CAPIEN0 : Input Capture Channel 0 Interrupt Enable Control
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
The flag CAPTF0 can trigger Input Capture interrupt Disabled
#1 : 1
The flag CAPTF0 can trigger Input Capture interrupt Enabled
End of enumeration elements list.
CAPIEN1 : Input Capture Channel 1 Interrupt Enable Control
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
The flag CAPTF1 can trigger Input Capture interrupt Disabled
#1 : 1
The flag CAPTF1 can trigger Input Capture interrupt Enabled
End of enumeration elements list.
CAPIEN2 : Input Capture Channel 2 Interrupt Enable Control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
The flag CAPTF2 can trigger Input Capture interrupt Disabled
#1 : 1
The flag CAPTF2 can trigger Input Capture interrupt Enabled
End of enumeration elements list.
OVIEN : CAPOVF Trigger Input Capture Interrupt Enable Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
The flag CAPOVF can trigger Input Capture interrupt Disabled
#1 : 1
The flag CAPOVF can trigger Input Capture interrupt Enabled
End of enumeration elements list.
CMPIEN : CAPCMPF Trigger Input Capture Interrupt Enable Control
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
The flag CAPCMPF can trigger Input Capture interrupt Disabled
#1 : 1
The flag CAPCMPF can trigger Input Capture interrupt Enabled
End of enumeration elements list.
CNTEN : Input Capture Counter Start Counting Control\nSetting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the .
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECAP_CNT stop counting
#1 : 1
ECAP_CNT starts up-counting
End of enumeration elements list.
CMPCLREN : Input Capture Counter Cleared by Compare-match Control
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled
#1 : 1
Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled
End of enumeration elements list.
CMPEN : Compare Function Enable Control\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
The compare function Disabled
#1 : 1
The compare function Enabled
End of enumeration elements list.
CAPEN : Input Capture Timer/Counter Enable Control
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input Capture function Disabled
#1 : 1
Input Capture function Enabled
End of enumeration elements list.
Input Capture Control Register 1
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGESEL0 : Channel 0 Captured Edge Selection\nInput capture0 can detect falling edge change only, rising edge change only or both edge change
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Detect rising edge only
#01 : 1
Detect falling edge only.\nDetect both rising and falling edge
End of enumeration elements list.
EDGESEL1 : Channel 1 Captured Edge Selection\nInput capture1 can detect falling edge change only, rising edge change only or both edge change
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Detect rising edge only
#01 : 1
Detect falling edge only.\nDetect both rising and falling edge
End of enumeration elements list.
EDGESEL2 : Channel 2 Captured Edge Selection\nInput capture2 can detect falling edge change only, rising edge change only or both edge changes
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Detect rising edge only
#01 : 1
Detect falling edge only.\nDetect both rising and falling edge
End of enumeration elements list.
CAP0RLDEN : Capture Counter's Reload Function Triggered by Event CAPTE0 Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The reload triggered by Event CAPTE0 Disabled
#1 : 1
The reload triggered by Event CAPTE0 Enabled
End of enumeration elements list.
CAP1RLDEN : Capture Counter's Reload Function Triggered by Event CAPTE1 Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The reload triggered by Event CAPTE1 Disabled
#1 : 1
The reload triggered by Event CAPTE1 Enabled
End of enumeration elements list.
CAP2RLDEN : Capture Counter's Reload Function Triggered by Event CAPTE2 Enable Bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The reload triggered by Event CAPTE2 Disabled
#1 : 1
The reload triggered by Event CAPTE2 Enabled
End of enumeration elements list.
OVRLDEN : Capture Counter's Reload Function Triggered by Overflow Enable Bit
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The reload triggered by CAPOV Disabled
#1 : 1
The reload triggered by CAPOV Enabled
End of enumeration elements list.
CLKSEL : Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0].
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
CAP_CLK/1
#001 : 1
CAP_CLK/4
#010 : 2
CAP_CLK/16
#011 : 3
CAP_CLK/32
#100 : 4
CAP_CLK/64
#101 : 5
CAP_CLK/96
#110 : 6
CAP_CLK/112
#111 : 7
CAP_CLK/128
End of enumeration elements list.
CNTSRCSEL : Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
CAP_CLK (default)
#01 : 1
CAP0
#10 : 2
CAP1
#11 : 3
CAP2
End of enumeration elements list.
CAP0CLREN : Capture Counter Cleared by Capture Event0 Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled
#1 : 1
Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled
End of enumeration elements list.
CAP1CLREN : Capture Counter Cleared by Capture Event1 Control
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled
#1 : 1
Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled
End of enumeration elements list.
CAP2CLREN : Capture Counter Cleared by Capture Event2 Control
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled
#1 : 1
Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled
End of enumeration elements list.
Input Capture Status Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTF0 : Input Capture Channel 0 Triggered Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. \nNote: This bit is only cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No valid edge change has been detected at CAP0 input since last clear
#1 : 1
At least a valid edge change has been detected at CAP0 input since last clear
End of enumeration elements list.
CAPTF1 : Input Capture Channel 1 Triggered Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. \nNote: This bit is only cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No valid edge change has been detected at CAP1 input since last clear
#1 : 1
At least a valid edge change has been detected at CAP1 input since last clear
End of enumeration elements list.
CAPTF2 : Input Capture Channel 2 Triggered Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. \nNote: This bit is only cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No valid edge change has been detected at CAP2 input since last clear
#1 : 1
At least a valid edge change has been detected at CAP2 input since last clear
End of enumeration elements list.
CAPCMPF : Input Capture Compare-match Flag\nIf the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECAP_CNT has not matched ECAP_CNTCMP value since last clear
#1 : 1
ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear
End of enumeration elements list.
CAPOVF : Input Capture Counter Overflow Flag\nFlag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.\nNote: This bit is only cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No overflow event has occurred since last clear
#1 : 1
Overflow event(s) has/have occurred since last clear
End of enumeration elements list.
CAP0 : Value of Input Channel 0, CAP0 (Read Only)\nReflecting the value of input channel 0, CAP0\nNote: The bit is read only and write is ignored.
bits : 8 - 8 (1 bit)
access : read-only
CAP1 : Value of Input Channel 1, CAP1 (Read Only)\nReflecting the value of input channel 1, CAP1\nNote: The bit is read only and write is ignored.
bits : 9 - 9 (1 bit)
access : read-only
CAP2 : Value of Input Channel 2, CAP2 (Read Only)\nReflecting the value of input channel 2, CAP2.\nNote: The bit is read only and write is ignored.
bits : 10 - 10 (1 bit)
access : read-only
Input Capture Hold Register 0
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOLD : Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register. Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
bits : 0 - 23 (24 bit)
access : read-write
Input Capture Hold Register 1
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Input Capture Hold Register 2
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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