\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x44 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x88 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
USCI Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNMODE : Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.\nNote: Other bit combinations are reserved.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
The USCI is disabled. All protocol related state machines are set to idle state
#001 : 1
The SPI protocol is selected
#010 : 2
The UART protocol is selected
#100 : 4
The I2C protocol is selected
End of enumeration elements list.
USCI Line Control Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSB : LSB First Transmission Selection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#1 : 1
The LSB, the bit 0 of data buffer, will be transmitted/received first
End of enumeration elements list.
DWIDTH : Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\n0x0: The data word contains 16 bits located at bit positions [15:0].\n0x1: Reserved.\n0x2: Reserved.\n0x3: Reserved.\n0x4: The data word contains 4 bits located at bit positions [3:0].\n0x5: The data word contains 5 bits located at bit positions [4:0].\n...\n0xF: The data word contains 15 bits located at bit positions [14:0].
bits : 8 - 11 (4 bit)
access : read-write
USCI Transmit Data Register
address_offset : 0x30 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDAT : Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.
bits : 0 - 15 (16 bit)
access : write-only
USCI Receive Data Register
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDAT : Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C.
bits : 0 - 15 (16 bit)
access : read-only
USCI Device Address Register 0
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEVADDR : Device Address\nIn I2C protocol, this bit field contains the programmed slave address. If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit. Then the second address byte is also compared to DEVADDR[7:0].\nNote 1: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode.\nNote 2: When software set 10'h000, the address can not be used.
bits : 0 - 9 (10 bit)
access : read-write
USCI Device Address Register 1
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USCI Device Address Mask Register 0
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRMSK : USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\nNote: The wake-up function can not use address mask.
bits : 0 - 9 (10 bit)
access : read-write
Enumeration:
0 : 0
Mask Disabled (the received corresponding register bit should be exact the same as address register.)
1 : 1
Mask Enabled (the received corresponding address bit is don't care.)
End of enumeration elements list.
USCI Device Address Mask Register 1
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USCI Wake-up Control Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKEN : Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up function Disabled
#1 : 1
Wake-up function Enabled
End of enumeration elements list.
WKADDREN : Wake-up Address Match Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The chip is woken up according data toggle
#1 : 1
The chip is woken up according address match
End of enumeration elements list.
USCI Wake-up Status Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKF : Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
USCI Protocol Control Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCFUNC : General Call Function
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
General Call Function Disabled
#1 : 1
General Call Function Enabled
End of enumeration elements list.
AA : Assert Acknowledge Control
bits : 1 - 1 (1 bit)
access : read-write
STO : I2C STOP Control
bits : 2 - 2 (1 bit)
access : read-write
STA : I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
bits : 3 - 3 (1 bit)
access : read-write
ADDR10EN : Address 10-bit Function Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Address match 10 bit function Disabled
#1 : 1
Address match 10 bit function Enabled
End of enumeration elements list.
PTRG : I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested. It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled.
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
#0 : 0
I2C's stretch disabled and the I2C protocol function will go ahead
#1 : 1
I2C's stretch active
End of enumeration elements list.
SCLOUTEN : SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low. This monitor will pull SCL to low until it has had time to respond to an I2C interrupt.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
SCL output will be forced high due to open drain mechanism
#1 : 1
I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt
End of enumeration elements list.
MONEN : Monitor Mode Enable Bit\nThis bit enables monitor mode. In monitor mode the SDA output will be put in high impedance mode. This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus.\nNote: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The monitor mode Disabled
#1 : 1
The monitor mode Enabled
End of enumeration elements list.
TOCNT : Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear. The time-out is enable when TOCNT bigger than 0. \nNote: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode.
bits : 16 - 25 (10 bit)
access : read-write
PROTEN : I2C Protocol Enable Bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C Protocol Disabled
#1 : 1
I2C Protocol Enabled
End of enumeration elements list.
USCI Protocol Interrupt Enable Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOIEN : Time-out Interrupt Enable Bit\nIn I2C protocol, this bit enables the interrupt generation in case of a time-out event.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The time-out interrupt Disabled
#1 : 1
The time-out interrupt Enabled
End of enumeration elements list.
STARIEN : START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The start condition interrupt Disabled
#1 : 1
The start condition interrupt Enabled
End of enumeration elements list.
STORIEN : STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The stop condition interrupt Disabled
#1 : 1
The stop condition interrupt Enabled
End of enumeration elements list.
NACKIEN : Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The non - acknowledge interrupt Disabled
#1 : 1
The non - acknowledge interrupt Enabled
End of enumeration elements list.
ARBLOIEN : Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The arbitration lost interrupt Disabled
#1 : 1
The arbitration lost interrupt Enabled
End of enumeration elements list.
ERRIEN : Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The error interrupt Disabled
#1 : 1
The error interrupt Enabled
End of enumeration elements list.
ACKIEN : Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The acknowledge interrupt Disabled
#1 : 1
The acknowledge interrupt Enabled
End of enumeration elements list.
USCI Protocol Status Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOIF : Time-out Interrupt Flag\nNote: It is cleared by software writing 1 into this bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
A time-out interrupt status has not occurred
#1 : 1
A time-out interrupt status has occurred
End of enumeration elements list.
ONBUSY : On Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bus is IDLE (both SCLK and SDA High)
#1 : 1
The bus is busy
End of enumeration elements list.
STARIF : Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode. However, this bit also indicates that a repeated start condition has been detected on slave mode.\nNote: It is cleared by software writing 1 into this bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
A start condition has not yet been detected
#1 : 1
A start condition has been detected
End of enumeration elements list.
STORIF : Stop Condition Received Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
A stop condition has not yet been detected
#1 : 1
A stop condition has been detected
End of enumeration elements list.
NACKIF : Non - Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
A non - acknowledge has not been received
#1 : 1
A non - acknowledge has been received
End of enumeration elements list.
ARBLOIF : Arbitration Lost Interrupt Flag\nNote: It is cleared by software writing 1 into this bit
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
An arbitration has not been lost
#1 : 1
An arbitration has been lost
End of enumeration elements list.
ERRIF : Error Interrupt Flag\nNote1: It is cleared by software writing 1 into this bit\nNote2: This bit is set for slave mode, and user must write 1 into STO register to the defined 'not addressed' slave mode.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
An I2C error has not been detected
#1 : 1
An I2C error has been detected
End of enumeration elements list.
ACKIF : Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
An acknowledge has not been received
#1 : 1
An acknowledge has been received
End of enumeration elements list.
SLASEL : Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The device is not selected as slave
#1 : 1
The device is selected as slave
End of enumeration elements list.
SLAREAD : Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
A slave R/W bit is 1 has not been detected
#1 : 1
A slave R/W bit is 1 has been detected
End of enumeration elements list.
WKAKDONE : Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't release when WKUPIF is set.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
The ACK bit cycle of address match frame isn't done
#1 : 1
The ACK bit cycle of address match frame is done in power-down
End of enumeration elements list.
WRSTSWK : Read/Write Status Bit in Address Wake-up Frame
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write command be record on the address match wake-up frame
#1 : 1
Read command be record on the address match wake-up frame
End of enumeration elements list.
BUSHANG : Bus Hang-up\nThis bit indicates bus hang-up status. There is 4-bit counter count when SCL hold high and refer fSAMP_CLK. The hang-up counter will count to overflow and set this bit when SDA is low. The counter will be reset by falling edge of SCL signal.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bus is normal status for transmission
#1 : 1
The bus is hang-up status for transmission
End of enumeration elements list.
ERRARBLO : Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor. The I2C can send start condition when ERRARBLO is set. Thus this bit doesn't be cared on slave mode.\nNote: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
The bus is normal status for transmission
#1 : 1
The bus is error arbitration lost status for transmission
End of enumeration elements list.
USCI Baud Rate Generator Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCLKSEL : Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Peripheral device clock fPCLK
#1 : 1
Reserved.
End of enumeration elements list.
PTCLKSEL : Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reference clock fREF_CLK
#1 : 1
fREF_CLK2 (its frequency is half of fREF_CLK)
End of enumeration elements list.
SPCLKSEL : Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
fSAMP_CLK = fDIV_CLK
#01 : 1
fSAMP_CLK = fPROT_CLK
#10 : 2
fSAMP_CLK = fSCLK
#11 : 3
fSAMP_CLK = fREF_CLK
End of enumeration elements list.
TMCNTEN : Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time measurement counter is Disabled
#1 : 1
Time measurement counter is Enabled
End of enumeration elements list.
TMCNTSRC : Time Measurement Counter Clock Source Selection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time measurement counter with fPROT_CLK
#1 : 1
Time measurement counter with fDIV_CLK
End of enumeration elements list.
PDSCNT : Pre-divider for Sample Counter
bits : 8 - 9 (2 bit)
access : read-write
DSCNT : Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
bits : 10 - 14 (5 bit)
access : read-write
CLKDIV : Clock Divider
bits : 16 - 25 (10 bit)
access : read-write
I2C Slave Match Address Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADMAT0 : USCI Address 0 Match Status Register\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
ADMAT1 : USCI Address 1 Match Status Register\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
I2C Timing Configure Control Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STCTL : Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode..
bits : 0 - 8 (9 bit)
access : read-write
HTCTL : Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge SDA edge in\ntransmission mode.
bits : 16 - 24 (9 bit)
access : read-write
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