\n

SCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

FVC_CTL (CTL)

FVC_BL2 (BL2)

FVC_BL32 (BL32)

FVC_BL33 (BL33)

FVC_UDF (UDF)

FVC_STS (STS)


FVC_CTL (CTL)

FVC Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FVC_CTL FVC_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT MONOEN WVCODE

INIT : FVC Init Bit\nSet to 1 to enable FVC\nThis bit is writable when FVC is at Reset state.\nNote: After set to one, this bit is cleared to zero automatically when FVC is back to Reset state.
bits : 0 - 0 (1 bit)
access : read-write

MONOEN : Monotonic Enable Bit\nSet to 1 to enable the monotonic mechanism of FVC.\nNote: This bit can be set to one but cannot be cleared to zero.
bits : 1 - 1 (1 bit)
access : read-write

WVCODE : Verification Code\nWhen write, VERIFY must be 0x7710
bits : 16 - 31 (16 bit)
access : read-write


FVC_BL2 (BL2)

BL2 Firmware Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FVC_BL2 FVC_BL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FW_VERSION WVCODE_RVCODE

FW_VERSION : Firmware Version\nRead: Indicate the current firmware version of BL2.\nWrite: Update the firmware version of BL2.\nThe maximum value is 63.
bits : 0 - 15 (16 bit)
access : read-write

WVCODE_RVCODE : Verification Code\nWhen write, VERIFY must be current firmware version number
bits : 16 - 31 (16 bit)
access : read-write


FVC_BL32 (BL32)

BL32 Firmware Control Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FVC_BL32 FVC_BL32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FW_VERSION WVCODE_RVCODE

FW_VERSION : Firmware Version\nRead: Indicate the current firmware version of BL32.\nWrite: Update the firmware version of BL32.\nThe maximum value is 63.
bits : 0 - 15 (16 bit)
access : read-write

WVCODE_RVCODE : Verification Code\nWhen write, VERIFY must be current firmware version number
bits : 16 - 31 (16 bit)
access : read-write


FVC_BL33 (BL33)

BL33 Firmware Control Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FVC_BL33 FVC_BL33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FW_VERSION WVCODE_RVCODE

FW_VERSION : Firmware Version\nRead: Indicate the current firmware version of BL33.\nWrite: Update the firmware version of BL33.\nThe maximum value is 255.
bits : 0 - 15 (16 bit)
access : read-write

WVCODE_RVCODE : Verification Code\nWhen write, VERIFY must be current firmware version number
bits : 16 - 31 (16 bit)
access : read-write


FVC_UDF (UDF)

User-defined Firmware Control Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FVC_UDF FVC_UDF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FW_VERSION WVCODE_RVCODE

FW_VERSION : Firmware Version\nRead: Indicate the current firmware version of user's firmware.\nWrite: Update the firmware version of user's firmware.\nThe maximum value is 255.
bits : 0 - 15 (16 bit)
access : read-write

WVCODE_RVCODE : Verification Code\nWhen write, VERIFY must be current firmware version number
bits : 16 - 31 (16 bit)
access : read-write


FVC_STS (STS)

FVC Status Register
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FVC_STS FVC_STS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY RDY

BUSY : FVC Busy Bit\nIndicates the FVC is at busy state.
bits : 0 - 0 (1 bit)
access : read-only

RDY : FVC Ready Bit\nIndicates the FVC is ready after the initial process.
bits : 1 - 1 (1 bit)
access : read-only



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