\n
address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x4C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
ISP Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPEN : ISP Enable Bit (Read Only)\nNote: This bit is read only to show ISP function enable.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#1 : 1
ISP function Enabled
End of enumeration elements list.
APUEN : APROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
APROM cannot be updated when the chip runs in APROM
#1 : 1
APROM can be updated when the chip runs in APROM
End of enumeration elements list.
CFGUEN : CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
CONFIG cannot be updated
#1 : 1
CONFIG can be updated
End of enumeration elements list.
LDUEN : LDROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
LDROM cannot be updated
#1 : 1
LDROM can be updated
End of enumeration elements list.
ISPFF : ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands\n(9) APROM is erased/programmed if KEYLOCK is set to 1\n(10) LDROM is erased/programmed if KEYLOCK is set to 1\n(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0 \n(12) Read any content of boot loader with ICE connection \n(13) The address of block erase and bank erase is not in APROM\n(14) ISP CMD in XOM region, except mass erase, page erase and chksum command\n(15) The wrong setting of page erase ISP CMD in XOM\n(16) Violate XOM setting one time protection\n(17) Page erase ISP CMD in Secure/Non-secure region setting page\n(18) Mass erase when MERASE (CFG0[13]) is disabled\n(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP\n(22)ISP conflict error\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write
INTEN : Secure ISP INT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.Before using INT,user needs to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP INT Disabled
#1 : 1
ISP INT Enabled
End of enumeration elements list.
ISP Trigger Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPGO : ISP Start Trigger (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP operation is finished
#1 : 1
ISP is progressed
End of enumeration elements list.
Data Flash Function Control
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCRAMEN : Data Scrambling Enable Bit\nUser can set this bit to enable Data scrambling protection on Data Flash.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data scrambling Disabled
#1 : 1
Data scrambling Enabled
End of enumeration elements list.
SILENTEN : Silent Access Enable Bit\nUser can set this bit to enable Silent access protection on Data Flash. Note that the Data Flash is formed as 4 pages of 1 Kbytes when silent access protection is enabled.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Silent access Disabled
#1 : 1
Silent access Enabled
End of enumeration elements list.
TMPPGMEN : Temper Attack Program Enable Bit\nUser can set this bit to control FMC to clear data (programming as zero) in Data Flash while temper attack event.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Temaper attack program Disabled
#1 : 1
Temaper attack program Enabled
End of enumeration elements list.
Data Flash Status
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TMPGMDONE : Data Flash Temper Attack Programming Done
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data Flash temper attack programming is not finished
#1 : 1
Data Flash temper attack programming is done, and user can write 1 to clear this bit
End of enumeration elements list.
TMPGMBUSY : Data Flash Temper Attack Programming Busy Status (Read Only)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data Flash temper attack programming is not busy
#1 : 1
Data Flash temper attack programming is busy
End of enumeration elements list.
Data Flash Scrambling Key
address_offset : 0x108 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SCRMKEY : Data Flash Scrambling Key (Write Only)\n32-bit user defined data scrambling key for Data Flash. When data scrambling is enabled (FMC_DTFSHCTL[0]), data in Data FLASH is scrambled when written and de-scrambled when read.
bits : 0 - 31 (32 bit)
access : write-only
Flash Access Time Control Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CACHEINV : Flash Cache Invalidation (Write Protect)\nNote 1: Write 1 to start cache invalidation. The value will be changed to 0 once the process finishes.\nNote 2: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash Cache Invalidation finished (default)
#1 : 1
Flash Cache Invalidation
End of enumeration elements list.
ISP Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPADDR : ISP Address\nThe M2354 series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.\nFor CRC32 Checksum Calculation command, this field is the Flash starting address for checksum calculation, 2 Kbytes alignment is necessary for CRC32 checksum calculation.\nFor Flash32-bit Program, ISP address needs word alignment (4-byte). For Flash 64-bit Program, ISP address needs double word alignment (8-byte).
bits : 0 - 31 (32 bit)
access : read-write
ISP Status Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPBUSY : ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
ISP operation is finished
#1 : 1
ISP is progressed
End of enumeration elements list.
FCYCDIS : Flash Access Cycle Auto-tuning Disable Flag (Read Only)\nThis bit is set if Flash access cycle auto-tunning function is disabled. The auto-tunning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Flash access cycle auto-tuning Enabled
#1 : 1
Flash access cyle auto-tuning Disabled
End of enumeration elements list.
PGFF : Flash Program with Fast Verification Flag (Read Only)\nThis bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP Flash erase or ISP read CID operation
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
Flash Program is success
#1 : 1
Flash Program is failed. Program data is different with data in the Flash memory
End of enumeration elements list.
ISPFF : ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands\n(9) APROM is erased/programmed if KEYLOCK is set to 1\n(10) LDROM is erased/programmed if KEYLOCK is set to 1\n(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0.\n(12) Read any content of boot loader with ICE connection \n(13) The address of block erase and bank erase is not in APROM\n(14) ISP CMD in XOM region, except mass erase, page erase and chksum command\n(15) The wrong setting of page erase ISP CMD in XOM\n(16) Violate XOM setting one time protection\n(17) Page erase ISP CMD in Secure/Non-secure region setting page\n(18) Mass erase when MERASE (CFG0[13]) is disabled\n(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP\n(22) ISP conflict error\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write
ALLONE : Flash All-one Verification Flag \nThis bit is set by hardware if all of Flash bits are 1, and clear if Flash bits are not all 1 after 'Run Flash All-One Verification' complete; this bit also can be clear by writing 1
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash bits are not all 1 after 'Run Flash All-One Verification' complete
#1 : 1
All of Flash bits are 1 after 'Run Flash All-One Verification' complete
End of enumeration elements list.
VECMAP : Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}
bits : 9 - 23 (15 bit)
access : read-only
INTFLAG : ISP Interuppt Flag\nNote: This function needs to be enabled by FMC_ISPCTRL[24].
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP Not Finished
#1 : 1
ISP done or ISPFF set
End of enumeration elements list.
ISPCERR : ISP Conflict Error\nThis bit shows when FMC is doing ISP operation.User can not access FMC_ISP_ADDR,FMC_ISPDAT,FMC_ISPCMD,FMC_ISPTRG. It would cause ISPFF.
bits : 28 - 28 (1 bit)
access : read-write
MIRBOUND : Mirror Boundary
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mirror Boundary Disabled
#1 : 1
Mirror Boundary Enabled
End of enumeration elements list.
FBS : Flash Bank Selection\nThis bit indicae which bank is selected to boot.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Booting from BANK0
#1 : 1
Booting from BANK1
End of enumeration elements list.
Flash Access Cycle Control Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CYCLE : Flash Access Cycle Control (Write Protect)\nThis register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1).When auto-tuning function disabled user needs to check the speed of HCLK and set the cycle 0.\nThe optimized HCLK working frequency range is81~96 MHz\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
CPU access with zero wait cycle ; Flash access cycle is 1;
#0001 : 1
CPU access with one wait cycle if cache miss; Flash access cycle is 1;
#0010 : 2
CPU access with two wait cycles if cache miss; Flash access cycle is 2;
#0011 : 3
CPU access with three wait cycles if cache miss; Flash access cycle is 3;
#0100 : 4
CPU access with four wait cycles if cache miss; Flash access cycle is 4;
End of enumeration elements list.
FADIS : Flash Access Cycle Auto-tuning Disable Bit (Write Protect)\nSet this bit to disable Flash access cycle auto-tuning function\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. When FMC is doning auto-tunning, it is consideredan ISP operation needs to monitor busy flag.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash access cycle auto-tuning Enabled
#1 : 1
Flash access cycle auto-tuning Disabled
End of enumeration elements list.
ISP Data Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT : ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write
ISP Data0 Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT0 : ISP Data 0\nThis register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data.
bits : 0 - 31 (32 bit)
access : read-write
ISP Data1 Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT1 : ISP Data 1\nThis register is the second 32-bit data for 64-bit/multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write
ISP Data2 Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT2 : ISP Data 2\nThis register is the third 32-bit data for multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write
ISP Data3 Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT3 : ISP Data 3\nThis register is the fourth 32-bit data for multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write
ISP Command Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : ISP Command\nThe ISP command table is shown below:\nThe other commands are invalid.
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x00 : 0
FLASH Read
0x04 : 4
Read Unique ID
0x08 : 8
Read Flash All-One Result
0x0b : 11
Read Company ID
0x0c : 12
Read Device ID
0x0d : 13
Read Checksum
0x21 : 33
FLASH 32-bit Program
0x22 : 34
FLASH Page Erase. Erase any page in two banks, except for OTP
0x23 : 35
FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1
0x25 : 37
FLASH Block Erase. Erase four pages alignment of APROM in BANK0 or BANK1
0x27 : 39
FLASH Multi-Word Program
0x28 : 40
Run Flash All-One Verification
0x2d : 45
Run Checksum Calculation
0x2e : 46
Vector Remap
0x40 : 64
FLASH 64-bit Read
0x61 : 97
FLASH 64-bit Program
End of enumeration elements list.
ISP Multi-program Status Register
address_offset : 0xC0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MPBUSY : ISP Multi-word Program Busy Flag (Read Only)\nWrite 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
ISP Multi-Word program operation is finished
#1 : 1
ISP Multi-Word program operation is progressed
End of enumeration elements list.
PPGO : ISP Multi-program Status (Read Only)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
ISP multi-word program operation is not active
#1 : 1
ISP multi-word program operation is in progress
End of enumeration elements list.
ISPFF : ISP Fail Flag (Read Only)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands.\n(9) APROM is erased/programmed if KEYLOCK is set to 1\n(10) LDROM is erased/programmed if KEYLOCK is set to 1\n(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0.\n(12) Read any content of boot loader with ICE connection \n(13) The address of block erase and bank erase is not in APROM\n(14) ISP CMD in XOM region, except mass erase, page erase and chksum command\n(15) The wrong setting of page erase ISP CMD in XOM\n(16) Violate XOM setting one time protection\n(17) Page erase ISP CMD in Secure/Non-secure region setting page\n(18) Mass erase when MERASE (CFG0[13]) is disabled\n(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP
bits : 2 - 2 (1 bit)
access : read-only
D0 : ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto-cleared to 0 when the FMC_MPDAT0 data is programmed to Flash complete.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
FMC_MPDAT0 register is empty, or program to Flash complete
#1 : 1
FMC_MPDAT0 register has been written, and not program to Flash complete
End of enumeration elements list.
D1 : ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto-cleared to 0 when the FMC_MPDAT1 data is programmed to Flash complete.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
FMC_MPDAT1 register is empty, or program to Flash complete
#1 : 1
FMC_MPDAT1 register has been written, and not program to Flash complete
End of enumeration elements list.
D2 : ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto-cleared to 0 when the FMC_MPDAT2 data is programmed to Flash complete.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
FMC_MPDAT2 register is empty, or program to Flash complete
#1 : 1
FMC_MPDAT2 register has been written, and not program to Flash complete
End of enumeration elements list.
D3 : ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto-cleared to 0 when the FMC_MPDAT3 data is programmed to Flash complete.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
FMC_MPDAT3 register is empty, or program to Flash complete
#1 : 1
FMC_MPDAT3 register has been written, and not program to Flash complete
End of enumeration elements list.
ISP Multi-program Address Register
address_offset : 0xC4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MPADDR : ISP Multi-word Program Address\nMPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\nMPADDR will keep the final ISP address when ISP multi-word program is complete.
bits : 0 - 31 (32 bit)
access : read-only
XOM Region 0 Status Register
address_offset : 0xD0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SIZE : XOM Region 0 Size (Page-aligned)\nSIZE is the page number of XOM Region 0.
bits : 0 - 7 (8 bit)
access : read-only
BASE : XOM Region 0 Base Address (Page-aligned)\nBASE is the base address of XOM Region 0.
bits : 8 - 31 (24 bit)
access : read-only
XOM Region 1 Status Register
address_offset : 0xD4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SIZE : XOM Region 1 Size (Page-aligned)\nSIZE is the page number of XOM Region 1.
bits : 0 - 7 (8 bit)
access : read-only
BASE : XOM Region 1 Base Address (Page-aligned)\nBASE is the base address of XOM Region 1.
bits : 8 - 31 (24 bit)
access : read-only
XOM Region 2 Status Register
address_offset : 0xD8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SIZE : XOM Region 2 Size (Page-aligned)\nSIZE is the page number of XOM Region 2.
bits : 0 - 7 (8 bit)
access : read-only
BASE : XOM Region 2 Base Address (Page-aligned)\nBASE is the base address of XOM Region 2.
bits : 8 - 31 (24 bit)
access : read-only
XOM Region 3 Status Register
address_offset : 0xDC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SIZE : XOM Region 3 Size (Page-aligned)\nSIZE is the page number of XOM Region 3.
bits : 0 - 7 (8 bit)
access : read-only
BASE : XOM Region 3 Base Address (Page-aligned)\nBASE is the base address of XOM Region 3.
bits : 8 - 31 (24 bit)
access : read-only
XOM Status Register
address_offset : 0xE0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
XOMR0ON : XOM Region 0 On\nXOM Region 0 active status.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No active
#1 : 1
XOM region 0 is active
End of enumeration elements list.
XOMR1ON : XOM Region 1 On\nXOM Region 1 active status.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
No active
#1 : 1
XOM region 1 is active
End of enumeration elements list.
XOMR2ON : XOM Region 2 On\nXOM Region 2 active status.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
No active
#1 : 1
XOM region 2 is active
End of enumeration elements list.
XOMR3ON : XOM Region 3 On\nXOM Region 3 active status.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
No active
#1 : 1
XOM region 3 is active
End of enumeration elements list.
XOMPEF : XOM Page Erase Function Fail\nXOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Sucess
#1 : 1
Fail
End of enumeration elements list.
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