\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x120 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x140 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x130 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x110 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x128 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x8 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection : not protected
RTC Initiation Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : RTC Active Status (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
RTC is at reset state
#1 : 1
RTC is at normal active state
End of enumeration elements list.
INIT : RTC Initiation (Write Only)\nWhen RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leave reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.\nThe INIT is a write-only field and read value will be always 0.
bits : 1 - 31 (31 bit)
access : write-only
RTC Calendar Loading Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAY : 1-Day Calendar Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write
TENDAY : 10-Day Calendar Digit (0~3)
bits : 4 - 5 (2 bit)
access : read-write
MON : 1-Month Calendar Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write
TENMON : 10-Month Calendar Digit (0~1)
bits : 12 - 12 (1 bit)
access : read-write
YEAR : 1-Year Calendar Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write
TENYEAR : 10-Year Calendar Digit (0~9)
bits : 20 - 23 (4 bit)
access : read-write
RTC 32.768 KHz Oscillator Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC32KEN : Enable LIRC32K Source
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
LIRC32K Disabled
#1 : 1
LIRC32K Enabled
End of enumeration elements list.
GAIN : Oscillator Gain Option\nUser can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption.
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
#000 : 0
L0 mode
#001 : 1
L1 mode
#010 : 2
L2 mode
#011 : 3
L3 mode
#100 : 4
L4 mode
#101 : 5
L5 mode
#110 : 6
L6 mode
#111 : 7
L7 mode(Default)
End of enumeration elements list.
C32KSEL : Clock 32K Source Selection
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from external low speed crystal oscillator (LXT)
#1 : 1
Clock source from internal low speed RC 32K oscillator (LIRC32K)
End of enumeration elements list.
RTCCKSEL : RTC Clock Source Selection
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from external low speed crystal oscillator (LXT) or internal low speed RC 32K oscillator (LIRC32K) depended on C32KSEL value
#1 : 1
Clock source from internal low speed RC oscillator (LIRC)
End of enumeration elements list.
IOCTLSEL : IO Pin Backup Control Selection\nWhen low speed 32 kHz oscillator is disabled or TAMPxEN is disabled, PF.4 pin (X32KO pin), PF.5 pin (X32KI pin) or PF.6~11 pin (TAMPERx pin) can be used as GPIO function. User can program IOCTLSEL to decide PF.4~11 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0/1 control register.\nNote: IOCTLSEL will automatically be set by hardware to 1 when system power is off and any writable RTC registers has been written at RTCCKEN(CLK_APBCLK0[1]) enabled.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.4~11 pin I/O function is controlled by GPIO module
#1 : 1
PF.4~11 pin I/O function is controlled by VBAT power domain
End of enumeration elements list.
RTC GPIO Control 0 Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPMODE0 : IO Operation Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.4 is input only mode
#01 : 1
PF.4 is output push pull mode
#10 : 2
PF.4 is open drain mode
#11 : 3
PF.4 is quasi-bidirectional mode
End of enumeration elements list.
DOUT0 : IO Output Data
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.4 output low
#1 : 1
PF.4 output high
End of enumeration elements list.
DINOFF0 : IO Pin Digital Input Path Disable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.4 digital input path Enabled
#1 : 1
PF.4 digital input path Disabled (digital input tied to low)
End of enumeration elements list.
PUSEL0 : IO Pull-up and Pull-down Enable Bits\nDetermine PF.4 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when OPMODE0 is set as input tri-state and open-drain mode.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.4 pull-up and pull-down Disabled
#01 : 1
PF.4 pull-up Enabled
#10 : 2
PF.4 pull-down Enabled
#11 : 3
PF.4 pull-up and pull-down Disabled
End of enumeration elements list.
OPMODE1 : IO Operation Mode
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.5 is input only mode
#01 : 1
PF.5 is output push pull mode
#10 : 2
PF.5 is open drain mode
#11 : 3
PF.5 is quasi-bidirectional mode
End of enumeration elements list.
DOUT1 : IO Output Data
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.5 output low
#1 : 1
PF.5 output high
End of enumeration elements list.
DINOFF1 : IO Pin Digital Input Path Disable Bit
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.5 digital input path Enabled
#1 : 1
PF.5 digital input path Disabled (digital input tied to low)
End of enumeration elements list.
PUSEL1 : IO Pull-up and Pull-down Enable Bits\nDetermine PF.5 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when OPMODE1 is set as input tri-state and open-drain mode.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.5 pull-up and pull-down Disabled
#01 : 1
PF.5 pull-up Enabled
#10 : 2
PF.5 pull-down Enabled
#11 : 3
PF.5 pull-up and pull-down Disabled
End of enumeration elements list.
OPMODE2 : IO Operation Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.6 is input only mode
#01 : 1
PF.6 is output push pull mode
#10 : 2
PF.6 is open drain mode
#11 : 3
PF.6 is quasi-bidirectional mode
End of enumeration elements list.
DOUT2 : IO Output Data
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.6 output low
#1 : 1
PF.6 output high
End of enumeration elements list.
DINOFF2 : IO Pin Digital Input Path Disable Bit
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.6 digital input path Enabled
#1 : 1
PF.6 digital input path Disabled (digital input tied to low)
End of enumeration elements list.
PUSEL2 : IO Pull-up and Pull-down Enable BitsDetermine PF.6 I/O Pull-up or Pull-down\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when OPMODE2 is set as input tri-state and open-drain mode.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.6 pull-up and pull-down Disabled
#01 : 1
PF.6 pull-up Enabled
#10 : 2
PF.6 pull-down Enabled
#11 : 3
PF.6 pull-up and pull-down Disabled
End of enumeration elements list.
OPMODE3 : IO Operation Mode
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.7 is input only mode
#01 : 1
PF.7 is output push pull mode
#10 : 2
PF.7 is open drain mode
#11 : 3
PF.7 is quasi-bidirectional mode
End of enumeration elements list.
DOUT3 : IO Output Data
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.7 output low
#1 : 1
PF.7 output high
End of enumeration elements list.
DINOFF3 : IO Pin Digital Input Path Disable Bit
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.7 digital input path Enabled
#1 : 1
PF.7 digital input path Disabled (digital input tied to low)
End of enumeration elements list.
PUSEL3 : IO Pull-up and Pull-down Enable Bits\nDetermine PF.7 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when OPMODE3 is set as input tri-state and open-drain mode.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.7 pull-up and pull-down Disabled
#01 : 1
PF.7 pull-up Enabled
#10 : 2
PF.7 pull-down Enabled
#11 : 3
PF.7 pull-up and pull-down Disabled
End of enumeration elements list.
RTC GPIO Control 1 Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPMODE4 : I/O Operation Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.8 is input only mode
#01 : 1
PF.8 is output push pull mode
#10 : 2
PF.8 is open drain mode
#11 : 3
PF.8 is quasi-bidirectional mode
End of enumeration elements list.
DOUT4 : I/O Output Data
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.8 output low
#1 : 1
PF.8 output high
End of enumeration elements list.
DINOFF4 : IO Pin Digital Input Path Disable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.8 digital input path Enabled
#1 : 1
PF.8 digital input path Disabled (digital input tied to low)
End of enumeration elements list.
PUSEL4 : I/O Pull-up and Pull-down Enable Bits\nDetermine PF.8 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when OPMODE4 is set as input tri-state and open-drain mode.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.8 pull-up and pull-down Disabled
#01 : 1
PF.8 pull-up Enabled
#10 : 2
PF.8 pull-down Enabled
#11 : 3
PF.8 pull-up and pull-down Disabled
End of enumeration elements list.
OPMODE5 : I/O Operation Mode
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.9 is input only mode
#01 : 1
PF.9 is output push pull mode
#10 : 2
PF.9 is open drain mode
#11 : 3
PF.9 is quasi-bidirectional mode
End of enumeration elements list.
DOUT5 : I/O Output Data
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.9 output low
#1 : 1
PF.9 output high
End of enumeration elements list.
DINOFF5 : IO Pin Digital Input Path Disable Bit
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.9 digital input path Enabled
#1 : 1
PF.9 digital input path Disabled (digital input tied to low)
End of enumeration elements list.
PUSEL5 : I/O Pull-up and Pull-down Enable Bits\nDetermine PF.9 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when OPMODE5 is set as input tri-state and open-drain mode.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.9 pull-up and pull-down Disabled
#01 : 1
PF.9 pull-up Enabled
#10 : 2
PF.9 pull-down Enabled
#11 : 3
PF.9 pull-up and pull-down Disabled
End of enumeration elements list.
OPMODE6 : I/O Operation Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.10 is input only mode
#01 : 1
PF.10 is output push pull mode
#10 : 2
PF.10 is open drain mode
#11 : 3
PF.10 is quasi-bidirectional mode
End of enumeration elements list.
DOUT6 : I/O Output Data
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.10 output low
#1 : 1
PF.10 output high
End of enumeration elements list.
DINOFF6 : IO Pin Digital Input Path Disable Bit
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.10 digital input path Enabled
#1 : 1
PF.10 digital input path Disabled (digital input tied to low)
End of enumeration elements list.
PUSEL6 : I/O Pull-up and Pull-down Enable Bits\nDetermine PF.10 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when OPMODE6 is set as input tri-state and open-drain mode.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.10 pull-up and pull-down Disabled
#01 : 1
PF.10 pull-up Enabled
#10 : 2
PF.10 pull-down Enabled
#11 : 3
PF.10 pull-up and pull-down Disabled
End of enumeration elements list.
OPMODE7 : IO Operation Mode
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.11 is input only mode
#01 : 1
PF.11 is output push pull mode
#10 : 2
PF.11 is open drain mode
#11 : 3
PF.11 is quasi-bidirectional mode
End of enumeration elements list.
DOUT7 : IO Output Data
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.11 output low
#1 : 1
PF.11 output high
End of enumeration elements list.
DINOFF7 : IO Pin Digital Input Path Disable Bit
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
PF.11 digital input path Enabled
#1 : 1
PF.11 digital input path Disabled (digital input tied to low)
End of enumeration elements list.
PUSEL7 : IO Pull-up and Pull-down Enable Bits\nDetermine PF.11 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register is only valid when OPMODE7 is set as input tri-state and open-drain mode.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
PF.11 pull-up and pull-down Disabled
#01 : 1
PF.11 pull-up Enabled
#10 : 2
PF.11 pull-down Enabled
#11 : 3
PF.11 pull-up and pull-down Disabled
End of enumeration elements list.
RTC Daylight Saving Time Control Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDHR : Add 1 Hour
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
RTC hour digit has been added one hour for summer time change
End of enumeration elements list.
SUBHR : Subtract 1 Hour
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
RTC hour digit has been subtracted one hour for winter time change
End of enumeration elements list.
DSBAK : Daylight Saving Back
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Daylight Saving Change is not performed
#1 : 1
Daylight Saving Change is performed
End of enumeration elements list.
RTC Tamper Pin Control Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DYN1ISS : Dynamic Pair 1 Input Source Select\nThis bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode.\nNote: This bit is effective only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper input is from Tamper 2
#1 : 1
Tamper input is from Tamper 0
End of enumeration elements list.
DYN2ISS : Dynamic Pair 2 Input Source Select\nThis bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode.\nNote: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper input is from Tamper 4
#1 : 1
Tamper input is from Tamper 0
End of enumeration elements list.
DYNSRC : Dynamic Reference Pattern\nThis fields determine the new reference pattern when current pattern run out in dynamic pair mode.\nNote: After this bit is modified, the SEEDRLD (RTC_TAMPCTL[4]) should be set.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The new reference pattern is generated by random number generator when the reference pattern run out
#1 : 1
The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out
End of enumeration elements list.
SEEDRLD : Reload New Seed for PRNG Engine\nSetting this bit, the tamper configuration will be reload.\nNote 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed.\nNote 2: The reference is RTC clock . Tamper detector need sync 2 ~ 3 RTC clock.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Generating key based on the current seed
#1 : 1
Reload new seed
End of enumeration elements list.
DYNRATE : Dynamic Change Rate\nThis item is choice the dynamic tamper output change rate.\nNote: After revising this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately.
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
#000 : 0
210 * RTC_CLK
#001 : 1
211 * RTC_CLK
#010 : 2
212 * RTC_CLK
#011 : 3
213 * RTC_CLK
#100 : 4
214 * RTC_CLK
#101 : 5
215 * RTC_CLK
#110 : 6
216 * RTC_CLK
#111 : 7
217 * RTC_CLK
End of enumeration elements list.
TAMP0EN : Tamper0 Detect Enable Bit\nNote: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 0 detect Disabled
#1 : 1
Tamper 0 detect Enabled
End of enumeration elements list.
TAMP0LV : Tamper 0 Level\nThis bit depends on level attribute of tamper pin for static tamper detection.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Detect voltage level is low
#1 : 1
Detect voltage level is high
End of enumeration elements list.
TAMP0DEN : Tamper 0 De-bounce Enable Bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 0 de-bounce Disabled
#1 : 1
Tamper 0 de-bounce Enabled, tamper detection pin will sync 1 RTC clock
End of enumeration elements list.
TAMP1EN : Tamper 1 Detect Enable Bit\nNote: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 1 detect Disabled
#1 : 1
Tamper 1 detect Enabled
End of enumeration elements list.
TAMP1LV : Tamper 1 Level\nThis bit depends on level attribute of tamper pin for static tamper detection.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Detect voltage level is low
#1 : 1
Detect voltage level is high
End of enumeration elements list.
TAMP1DEN : Tamper 1 De-bounce Enable Bit
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 1 de-bounce Disabled
#1 : 1
Tamper 1 de-bounce Enabled, tamper detection pin will sync 1 RTC clock
End of enumeration elements list.
DYNPR0EN : Dynamic Pair 0 Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Static detect
#1 : 1
Dynamic detect
End of enumeration elements list.
TAMP2EN : Tamper 2 Detect Enable Bit\nNote: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 2 detect Disabled
#1 : 1
Tamper 2 detect Enabled
End of enumeration elements list.
TAMP2LV : Tamper 2 Level\nThis bit depends on level attribute of tamper pin for static tamper detection.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Detect voltage level is low
#1 : 1
Detect voltage level is high
End of enumeration elements list.
TAMP2DEN : Tamper 2 De-bounce Enable Bit
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 2 de-bounce Disabled
#1 : 1
Tamper 2 de-bounce Enabled, tamper detection pin will sync 1 RTC clock
End of enumeration elements list.
TAMP3EN : Tamper 3 Detect Enable Bit\nNote: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 3 detect Disabled
#1 : 1
Tamper 3 detect Enabled
End of enumeration elements list.
TAMP3LV : Tamper 3 Level\nThis bit depends on level attribute of tamper pin for static tamper detection.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Detect voltage level is low
#1 : 1
Detect voltage level is high
End of enumeration elements list.
TAMP3DEN : Tamper 3 De-bounce Enable Bit
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 3 de-bounce Disabled
#1 : 1
Tamper 3 de-bounce Enabled, tamper detection pin will sync 1 RTC clock
End of enumeration elements list.
DYNPR1EN : Dynamic Pair 1 Enable Bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Static detect
#1 : 1
Dynamic detect
End of enumeration elements list.
TAMP4EN : Tamper4 Detect Enable Bit\nNote: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 4 detect Disabled
#1 : 1
Tamper 4 detect Enabled
End of enumeration elements list.
TAMP4LV : Tamper 4 Level\nThis bit depends on level attribute of tamper pin for static tamper detection.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Detect voltage level is low
#1 : 1
Detect voltage level is high
End of enumeration elements list.
TAMP4DEN : Tamper 4 De-bounce Enable Bit
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 4 de-bounce Disabled
#1 : 1
Tamper 4 de-bounce Enabled, tamper detection pin will sync 1 RTC clock
End of enumeration elements list.
TAMP5EN : Tamper 5 Detect Enable Bit\nNote: The reference is RTC-clock . Tamper detector need sync 2 ~ 3 RTC-clock.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 5 detect Disabled
#1 : 1
Tamper 5 detect Enabled
End of enumeration elements list.
TAMP5LV : Tamper 5 Level\nThis bit depends on level attribute of tamper pin for static tamper detection.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Detect voltage level is low
#1 : 1
Detect voltage level is high
End of enumeration elements list.
TAMP5DEN : Tamper 5 De-bounce Enable Bit
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 5 de-bounce Disabled
#1 : 1
Tamper 5 de-bounce Enabled, tamper detection pin will sync 1 RTC clock
End of enumeration elements list.
DYNPR2EN : Dynamic Pair 2 Enable Bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Static detect
#1 : 1
Dynamic detect
End of enumeration elements list.
RTC Tamper Dynamic Seed Register
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEED : Seed Value
bits : 0 - 31 (32 bit)
access : read-write
RTC Tamper Time Register
address_offset : 0x130 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC : 1-Sec Time Digit of TAMPER Time (0~9)
bits : 0 - 3 (4 bit)
access : read-only
TENSEC : 10-Sec Time Digit of TAMPER Time (0~5)
bits : 4 - 6 (3 bit)
access : read-only
MIN : 1-Min Time Digit of TAMPER Time (0~9)
bits : 8 - 11 (4 bit)
access : read-only
TENMIN : 10-Min Time Digit of TAMPER Time (0~5)
bits : 12 - 14 (3 bit)
access : read-only
HR : 1-Hour Time Digit of TAMPER Time (0~9)
bits : 16 - 19 (4 bit)
access : read-only
TENHR : 10-hour Time Digit of TAMPER Time (0~2) \nNote: 24-hour time scale only.
bits : 20 - 21 (2 bit)
access : read-only
RTC Tamper Calendar Register
address_offset : 0x134 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DAY : 1-Day Calendar Digit of TAMPER Calendar (0~9)
bits : 0 - 3 (4 bit)
access : read-only
TENDAY : 10-Day Calendar Digit of TAMPER Calendar (0~3)
bits : 4 - 5 (2 bit)
access : read-only
MON : 1-Month Calendar Digit of TAMPER Calendar (0~9)
bits : 8 - 11 (4 bit)
access : read-only
TENMON : 10-Month Calendar Digit of TAMPER Calendar (0~1)
bits : 12 - 12 (1 bit)
access : read-only
YEAR : 1-Year Calendar Digit of TAMPER Calendar (0~9)
bits : 16 - 19 (4 bit)
access : read-only
TENYEAR : 10-Year Calendar Digit of TAMPER Calendar (0~9)
bits : 20 - 23 (4 bit)
access : read-only
RTC Time Scale Selection Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
_24HEN : 24-hour / 12-hour Time Scale Selection\nThe RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
12-hour time scale with AM and PM indication selected
#1 : 1
24-hour time scale selected
End of enumeration elements list.
DCOMPEN : Dynamic Compensation Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dynamic Compensation Disabled
#1 : 1
Dynamic Compensation Enabled
End of enumeration elements list.
Clock Fail Detector Control Register
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LXTFDEN : LXT Clock Fail/Stop Detector Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
LXT clock Fail/Stop detector Disabled
#1 : 1
LXT clock Fail/Stop detector Enabled
End of enumeration elements list.
LXTFSW : LXT Clock Fail Detector Switch LIRC32K Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
LXT clock Fail switch LIRC32K Disabled
#1 : 1
LXT clock Fail detector rise, RTC clock source switch from LIRC32K
End of enumeration elements list.
LXTSPSW : LXT Clock Stop Detector Switch LIRC32K Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
LXT clock Stop switch LIRC32K Disabled
#1 : 1
LXT clock Stop detector rise, RTC clock source switch from LIRC32K
End of enumeration elements list.
SWLIRCF : LXT Clock Detector Fail/Stop Switch LIRC32K Flag (Read Only)
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicate RTC clock source from LXT
#1 : 1
Indicate RTC clock source from LIRC32K
End of enumeration elements list.
LXTSLOWF : LXT Slower Than LIRC32K Flag (Read Only) \nNote: LXTSLOWF is vaild during CLKSPIF (RTC_INTSTS[25]) or CLKFIF (RTC_INTSTS[24]) rising.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
LXT frequency faster than LIRC32K
#1 : 1
LXT frequency is slowly
End of enumeration elements list.
Clock Frequency Detector Boundary Register
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOPBD : LXT Clock Stop Frequency Detector Stop Boundary\nThe bits define the stop value of frequency monitor window.\nWhen LXT frequency monitor counter lower than STOPBD, the LXT frequency detect Stop interrupt flag will set to 1.\nNote: The boundary is defined as the maximun value of LXT among 256 LIRC32K clock time.
bits : 0 - 7 (8 bit)
access : read-write
FAILBD : LXT Clock Frequency Detector Fail Boundary\nThe bits define the fail value of frequency monitor window.\nWhen LXT frequency monitor counter lower than FAILBD, the LXT frequency detect fail interrupt flag will set to 1.\nNote: The boundary is defined as the minimun value of LXT among 256 LIRC32K clock time.
bits : 16 - 23 (8 bit)
access : read-write
RTC Day of the Week Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WEEKDAY : Day of the Week Register
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Sunday
#001 : 1
Monday
#010 : 2
Tuesday
#011 : 3
Wednesday
#100 : 4
Thursday
#101 : 5
Friday
#110 : 6
Saturday
#111 : 7
Reserved.
End of enumeration elements list.
RTC Time Alarm Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : 1-Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write
TENSEC : 10-Sec Time Digit of Alarm Setting (0~5)
bits : 4 - 6 (3 bit)
access : read-write
MIN : 1-Min Time Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write
TENMIN : 10-Min Time Digit of Alarm Setting (0~5)
bits : 12 - 14 (3 bit)
access : read-write
HR : 1-Hour Time Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write
TENHR : 10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
bits : 20 - 21 (2 bit)
access : read-write
RTC Calendar Alarm Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAY : 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write
TENDAY : 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 4 - 5 (2 bit)
access : read-write
MON : 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write
TENMON : 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 12 - 12 (1 bit)
access : read-write
YEAR : 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write
TENYEAR : 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 20 - 23 (4 bit)
access : read-write
RTC Leap Year Indicator Register
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LEAPYEAR : Leap Year Indication (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
This year is not a leap year
#1 : 1
This year is leap year
End of enumeration elements list.
RTC Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALMIEN : Alarm Interrupt Enable Bit\nSet ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC Alarm interrupt Disabled
#1 : 1
RTC Alarm interrupt Enabled
End of enumeration elements list.
TICKIEN : Time Tick Interrupt Enable Bit\nSet TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC Time Tick interrupt Disabled
#1 : 1
RTC Time Tick interrupt Enabled
End of enumeration elements list.
TAMP0IEN : Tamper 0 Interrupt Enable Bit\nSet TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 0 interrupt Disabled
#1 : 1
Tamper 0 interrupt Enabled
End of enumeration elements list.
TAMP1IEN : Tamper 1 or Pair 0 Interrupt Enable Bit\nSet TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 1 or Pair 0 interrupt Disabled
#1 : 1
Tamper 1 or Pair 0 interrupt Enabled
End of enumeration elements list.
TAMP2IEN : Tamper 2 Interrupt Enable Bit\nSet TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 2 interrupt Disabled
#1 : 1
Tamper 2 interrupt Enabled
End of enumeration elements list.
TAMP3IEN : Tamper 3 or Pair 1 Interrupt Enable Bit\nSet TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 3 or Pair 1 interrupt Disabled
#1 : 1
Tamper 3 or Pair 1 interrupt Enabled
End of enumeration elements list.
TAMP4IEN : Tamper 4 Interrupt Enable Bit\nSet TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 4 interrupt Disabled
#1 : 1
Tamper 4 interrupt Enabled
End of enumeration elements list.
TAMP5IEN : Tamper 5 or Pair 2 Interrupt Enable Bit\nSet TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tamper 5 or Pair 2 interrupt Disabled
#1 : 1
Tamper 5 or Pair 2 interrupt Enabled
End of enumeration elements list.
CLKFIEN : LXT Clock Frequency Monitor Fail Interrupt Enable Bit
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
LXT Frequency Fail interrupt Disabled
#1 : 1
LXT Frequency Fail interrupt Enabled
End of enumeration elements list.
CLKSTIEN : LXT Clock Frequency Monitor Stop Interrupt Enable Bit
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
LXT Frequency Stop interrupt Disabled
#1 : 1
LXT Frequency Stop interrupt Enabled
End of enumeration elements list.
RTC Interrupt Status Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALMIF : RTC Alarm Interrupt Flag\nNote: Write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Alarm condition is not matched
#1 : 1
Alarm condition is matched
End of enumeration elements list.
TICKIF : RTC Time Tick Interrupt Flag\nNote: Write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tick condition did not occur
#1 : 1
Tick condition occurred
End of enumeration elements list.
TAMP0IF : Tamper 0 Interrupt Flag\nThis bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]).\nNote 1: Write 1 to clear this bit.\nNote 2: This interrupt flag will be generated again when Tamper setting condition is not restoration.\nNote 3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Tamper 0 interrupt flag is generated
#1 : 1
Tamper 0 interrupt flag is generated
End of enumeration elements list.
TAMP1IF : Tamper 1 or Pair 0 Interrupt Flag\nThis bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated.\nNote 1: Write 1 to clear this bit.\nNote 2: This interrupt flag will be generated again when Tamper setting condition is not restoration.\nNote 3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Tamper 1 or Pair 0 interrupt flag is generated
#1 : 1
Tamper 1 or Pair 0 interrupt flag is generated
End of enumeration elements list.
TAMP2IF : Tamper 2 Interrupt Flag\nThis bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]).\nNote 1: Write 1 to clear this bit.\nNote 2: This interrupt flag will be generated agan when Tamper setting condition is not restoration.\nNote 3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Tamper 2 interrupt flag is generated
#1 : 1
Tamper 2 interrupt flag is generated
End of enumeration elements list.
TAMP3IF : Tamper 3 or Pair 1 Interrupt Flag\nThis bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated or TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated.\nNote 1: Write 1 to clear this bit.\nNote 2: This interrupt flag will be generated again when Tamper setting condition is not restoration.\nNote 3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Tamper 3 or Pair 1 interrupt flag is generated
#1 : 1
Tamper 3 or Pair 1 interrupt flag is generated
End of enumeration elements list.
TAMP4IF : Tamper 4 Interrupt Flag\nThis bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]).\nNote 1: Write 1 to clear this bit.\nNote 2: This interrupt flag will be generated again when Tamper setting condition is not restoration.\nNote 3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Tamper 4 interrupt flag is generated
#1 : 1
Tamper 4 interrupt flag is generated
End of enumeration elements list.
TAMP5IF : Tamper 5 or Pair 2 Interrupt Flag\nThis bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated or TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated.\nNote 1: Write 1 to clear this bit.\nNote 2: This interrupt flag will be generated again when Tamper setting condition is not restoration.\nNote 3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Tamper 5 or Pair 2 interrupt flag is generated
#1 : 1
Tamper 5 or Pair 2 interrupt flag is generated
End of enumeration elements list.
CLKFIF : LXT Clock Frequency Monitor Fail Interrupt Flag\nNote 1: Write 1 to clear the bit to 0.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
LXT frequency is normal
#1 : 1
LXT frequency is abnormal
End of enumeration elements list.
CLKSPIF : LXT Clock Frequency Monitor Stop Interrupt Flag\nNote 1: Write 1 to clear the bit to 0.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
LXT frequency is normal
#1 : 1
LXT frequency is almost stop
End of enumeration elements list.
RTC Time Tick Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TICK : Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Time tick is 1 second
#001 : 1
Time tick is 1/2 second
#010 : 2
Time tick is 1/4 second
#011 : 3
Time tick is 1/8 second
#100 : 4
Time tick is 1/16 second
#101 : 5
Time tick is 1/32 second
#110 : 6
Time tick is 1/64 second
#111 : 7
Time tick is 1/128 second
End of enumeration elements list.
RTC Time Alarm Mask Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSEC : Mask 1-Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 0 (1 bit)
access : read-write
MTENSEC : Mask 10-Sec Time Digit of Alarm Setting (0~5)
bits : 1 - 1 (1 bit)
access : read-write
MMIN : Mask 1-Min Time Digit of Alarm Setting (0~9)
bits : 2 - 2 (1 bit)
access : read-write
MTENMIN : Mask 10-Min Time Digit of Alarm Setting (0~5)
bits : 3 - 3 (1 bit)
access : read-write
MHR : Mask 1-Hour Time Digit of Alarm Setting (0~9)
bits : 4 - 4 (1 bit)
access : read-write
MTENHR : Mask 10-Hour Time Digit of Alarm Setting (0~2)
bits : 5 - 5 (1 bit)
access : read-write
RTC Calendar Alarm Mask Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDAY : Mask 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 0 (1 bit)
access : read-write
MTENDAY : Mask 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 1 - 1 (1 bit)
access : read-write
MMON : Mask 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 2 - 2 (1 bit)
access : read-write
MTENMON : Mask 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 3 - 3 (1 bit)
access : read-write
MYEAR : Mask 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 4 - 4 (1 bit)
access : read-write
MTENYEAR : Mask 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 5 - 5 (1 bit)
access : read-write
RTC Spare Functional Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPRRWEN : Spare Register Enable Bit\nNote: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Spare register Disabled
#1 : 1
Spare register Enabled
End of enumeration elements list.
SPRCSTS : SPR Clear Flag \nThis bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify tamper event is detected.\nNote 1: Write 1 to clear this bit.\nNote 2: This bit keeps 1 when RTC_INTSTS[13:8] is not equal to 0.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Spare register content is not cleared
#1 : 1
Spare register content is cleared
End of enumeration elements list.
LXTFCLR : LXT Clock Fail/Stop to Clear Spare Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
LXT Fail/Stop to clear Spare register content Disabled.
#1 : 1
LXT Fail/Stop to clear Spare register content Enabled
End of enumeration elements list.
RTC Spare Register 0
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPARE : Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically in the following conditions, a tamper pin event is detected, LXT clock fail/stop event occurs if LXTFCLR(RTC_SPRCTL[16]) is 1, or after Flash mass operation.
bits : 0 - 31 (32 bit)
access : read-write
RTC Spare Register 1
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 2
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 3
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 4
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 5
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 6
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 7
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 8
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 9
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 10
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 11
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 12
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 13
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 14
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 15
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Frequency Compensation Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRACTION : Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number.
bits : 0 - 5 (6 bit)
access : read-write
INTEGER : Integer Part
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Integer part of detected value is 32752
#00001 : 1
Integer part of detected value is 32753
#00010 : 2
Integer part of detected value is 32754
#00011 : 3
Integer part of detected value is 32755
#00100 : 4
Integer part of detected value is 32756
#00101 : 5
Integer part of detected value is 32757
#00110 : 6
Integer part of detected value is 32758
#00111 : 7
Integer part of detected value is 32759
#01000 : 8
Integer part of detected value is 32760
#01001 : 9
Integer part of detected value is 32761
#01010 : 10
Integer part of detected value is 32762
#01011 : 11
Integer part of detected value is 32763
#01100 : 12
Integer part of detected value is 32764
#01101 : 13
Integer part of detected value is 32765
#01110 : 14
Integer part of detected value is 32766
#01111 : 15
Integer part of detected value is 32767
#10000 : 16
Integer part of detected value is 32768
#10001 : 17
Integer part of detected value is 32769
#10010 : 18
Integer part of detected value is 32770
#10011 : 19
Integer part of detected value is 32771
#10100 : 20
Integer part of detected value is 32772
#10101 : 21
Integer part of detected value is 32773
#10110 : 22
Integer part of detected value is 32774
#10111 : 23
Integer part of detected value is 32775
#11000 : 24
Integer part of detected value is 32776
#11001 : 25
Integer part of detected value is 32777
#11010 : 26
Integer part of detected value is 32778
#11011 : 27
Integer part of detected value is 32779
#11100 : 28
Integer part of detected value is 32780
#11101 : 29
Integer part of detected value is 32781
#11110 : 30
Integer part of detected value is 32782
#11111 : 31
Integer part of detected value is 32783
End of enumeration elements list.
FCRBUSY : Frequency Compensation Register Write Operation Busy (Read Only)\nNote: This bit is only used when DCOMPEN(RTC_CLKFMT[16]) is enabled.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
The new register write operation is acceptable
#1 : 1
The last write operation is in progress and new register write operation prohibited
End of enumeration elements list.
RTC Spare Register 16
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 17
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 18
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Spare Register 19
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Time Loading Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : 1-Sec Time Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write
TENSEC : 10-Sec Time Digit (0~5)
bits : 4 - 6 (3 bit)
access : read-write
MIN : 1-Min Time Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write
TENMIN : 10-Min Time Digit (0~5)
bits : 12 - 14 (3 bit)
access : read-write
HR : 1-Hour Time Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write
TENHR : 10-Hour Time Digit (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
bits : 20 - 21 (2 bit)
access : read-write
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