Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xB0 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
SHA/HMAC Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : SHA/HMAC Engine Start\nNote: This bit is always 0 when it's read back.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Start SHA/HMAC engine. BUSY flag will be set
End of enumeration elements list.
STOP : SHA/HMAC Engine Stop\nNote: This bit is always 0 when it's read back.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Stop SHA/HMAC engine
End of enumeration elements list.
DMAFIRST : SHA/HMAC First Block in Cascadefunction\nThis bit must be set as feeding in first byte of data.
bits : 4 - 4 (1 bit)
access : read-write
DMALAST : SHA/HMAC Last Block\nThis bit must be set as feeding in last byte of data.
bits : 5 - 5 (1 bit)
access : read-write
DMACSCAD : SHA/HMAC Engine DMA with Cascade Mode
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA cascade function Disabled
#1 : 1
In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation
End of enumeration elements list.
DMAEN : SHA/HMAC Engine DMA Enable Bit\nSHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
SHA/HMAC DMA engine Disabled
#1 : 1
SHA/HMAC DMA engine Enabled
End of enumeration elements list.
OPMODE : SHA/HMAC Engine Operation Modes\n0x0xx: SHA-160\n0x100: SHA-256\n0x101: SHA-224\n0x110: SHA-512\n0x111: SHA-384
bits : 8 - 10 (3 bit)
access : read-write
HMACEN : HMAC_SHA Engine Operating Mode
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Execute SHA function
#1 : 1
Execute HMAC function
End of enumeration elements list.
OUTSWAP : SHA/HMAC Engine Output Data Swap
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
INSWAP : SHA/HMAC Engine Input Data Swap
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
SHA/HMAC Output Feedback Data 2
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 22 After SHA/HMAC Operation
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 23 After SHA/HMAC Operation
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 24 After SHA/HMAC Operation
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 25 After SHA/HMAC Operation
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 26 After SHA/HMAC Operation
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 27 After SHA/HMAC Operation
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 28 After SHA/HMAC Operation
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 29 After SHA/HMAC Operation
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 30 After SHA/HMAC Operation
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 31 After SHA/HMAC Operation
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 32 After SHA/HMAC Operation
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 33 After SHA/HMAC Operation
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 34 After SHA/HMAC Operation
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 35 After SHA/HMAC Operation
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 36 After SHA/HMAC Operation
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 37 After SHA/HMAC Operation
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 3
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 38 After SHA/HMAC Operation
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 39 After SHA/HMAC Operation
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 40 After SHA/HMAC Operation
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 41 After SHA/HMAC Operation
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 42 After SHA/HMAC Operation
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 43 After SHA/HMAC Operation
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 44 After SHA/HMAC Operation
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 45 After SHA/HMAC Operation
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 46 After SHA/HMAC Operation
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 47 After SHA/HMAC Operation
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 48 After SHA/HMAC Operation
address_offset : 0x168 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 49 After SHA/HMAC Operation
address_offset : 0x16C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 50 After SHA/HMAC Operation
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 51 After SHA/HMAC Operation
address_offset : 0x174 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 52 After SHA/HMAC Operation
address_offset : 0x178 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 53 After SHA/HMAC Operation
address_offset : 0x17C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 4
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 5
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 6
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 7
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 8
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 9
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 10
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 11
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 12
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 13
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Status Flag
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : SHA/HMAC Engine Busy
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
SHA/HMAC engine is idle or finished
#1 : 1
SHA/HMAC engine is busy
End of enumeration elements list.
DMABUSY : SHA/HMAC Engine DMA Busy Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
SHA/HMAC DMA engine is idle or finished
#1 : 1
SHA/HMAC DMA engine is busy
End of enumeration elements list.
DMAERR : SHA/HMAC Engine DMA Error Flag
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
Show the SHA/HMAC engine access normal
#1 : 1
Show the SHA/HMAC engine access error
End of enumeration elements list.
KSERR : HMAC Engine Access Key Store Error Flag
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Access error will stop HMAC engine
End of enumeration elements list.
DATINREQ : SHA/HMAC Non-dMA Mode Data Input Request
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
No effect
#1 : 1
Request SHA/HMAC Non-DMA mode data input
End of enumeration elements list.
SHA/HMAC Output Feedback Data 14
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 15
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Key Byte Count Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEYCNT : SHA/HMAC Key Byte Count\nThe CRYPTO_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates. The register is 32-bit and the maximum byte count is 4G bytes. It can be read and written. \nWriting to the register CRYPTO_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesn't affect the current SHA/HMAC operation. But the value of CRYPTO_HMAC_KEYCNT will be updated later on. Consequently, software can prepare the key count for the next SHA/HMAC operation.
bits : 0 - 31 (32 bit)
access : read-write
SHA/HMAC DMA Source Address Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : SHA/HMAC DMA Source Address\nThe SHA/HMAC accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The CRYPTO_HMAC_SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the SHA/HMAC accelerator can read the plain text from SRAM memory space and do SHA/HMAC operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of CRYPTO_HMAC_SADDR are ignored.\nCRYPTO_HMAC_SADDR can be read and written. Writing to CRYPTO_HMAC_SADDR while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation. But the value of CRYPTO_HMAC_SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next SHA/HMAC operation.\nIn DMA mode, software can update the next CRYPTO_HMAC_SADDR before triggering START.\nCRYPTO_HMAC_SADDR and CRYPTO_HMAC_DADDR can be the same in the value.
bits : 0 - 31 (32 bit)
access : read-write
SHA/HMAC Byte Count Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMACNT : SHA/HMAC Operation Byte Count\nThe CRYPTO_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode. The CRYPTO_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes.\nCRYPTO_HMAC_DMACNT can be read and written. Writing to CRYPTO_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation. But the value of CRYPTO_HMAC_DMACNT will be updated later on. Consequently, software can prepare the byte count of data for the next SHA/HMAC operation.\nIn Non-DMA mode, CRYPTO_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data.
bits : 0 - 31 (32 bit)
access : read-write
SHA/HMAC Engine Non-dMA Mode Data Input Port Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATIN : SHA/HMAC Engine Input Port\nCPU feeds data to SHA/HMAC engine through this port by checking CRYPTO_HMAC_STS. Feed data as DATINREQ is 1.
bits : 0 - 31 (32 bit)
access : read-write
SHA/HMAC Output Feedback Data 0 After SHA/HMAC Operation
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FDBCK : SHA/HMAC Feedback Information\nThe feedback value is 1728 bits in size.\nThe SHA/HMAC engine uses the data from CRYPTO_HMAC_FDBCKx as the data inputted to CRYPTO_HMAC_FDBCKx for the next block in DMA cascade mode.\nThe SHA/HMAC engine outputs feedback information for initial setting in the next block's operation. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to CRYPTO_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting.
bits : 0 - 31 (32 bit)
access : read-write
SHA/HMAC Output Feedback Data 1 After SHA/HMAC Operation
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 2 After SHA/HMAC Operation
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 3 After SHA/HMAC Operation
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 4 After SHA/HMAC Operation
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 5 After SHA/HMAC Operation
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 6 After SHA/HMAC Operation
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 7 After SHA/HMAC Operation
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 8 After SHA/HMAC Operation
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 9 After SHA/HMAC Operation
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 0
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DGST : SHA/HMAC Output Feedback Data Output Register\nFor SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7.\nFor SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11.\nFor SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15.
bits : 0 - 31 (32 bit)
access : read-only
SHA/HMAC Output Feedback Data 10 After SHA/HMAC Operation
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 11 After SHA/HMAC Operation
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 12 After SHA/HMAC Operation
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 13 After SHA/HMAC Operation
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 14 After SHA/HMAC Operation
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 15 After SHA/HMAC Operation
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 16 After SHA/HMAC Operation
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 17 After SHA/HMAC Operation
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 18 After SHA/HMAC Operation
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 19 After SHA/HMAC Operation
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 20 After SHA/HMAC Operation
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 21 After SHA/HMAC Operation
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Output Feedback Data 1
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HMAC Key Control Register
address_offset : 0xC30 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
NUM : Read Key Number\nThe key number is sent to key store
bits : 0 - 4 (5 bit)
access : write-only
RSRC : Read Key Destination
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
#0 : 0
Key is read from HMAC registers
#1 : 1
Key is read from key store
End of enumeration elements list.
RSSRC : Read Key Store Destination
bits : 6 - 7 (2 bit)
access : write-only
Enumeration:
#00 : 0
Key is read from the SRAM of key store
#01 : 1
Key is read from the Flash of key store
#10 : 2
Key is read from the OTP of key store
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.