Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xB0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD4 Bytes (0x0)
size : 0xDC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xEC0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
AES Engine Output Feedback Data After Cryptographic Operation
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FDBCK : AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AESn_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for IV in the next block's operation. Software can use this feedback information to implement more than four DMA channels. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to CRYPTO_AESn_IVx in the same channel operation, and then continue the operation with the original setting.
bits : 0 - 31 (32 bit)
access : read-only
AES Key Word 1 Register for Channel 1
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 2 Register for Channel 1
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 3 Register for Channel 1
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 4 Register for Channel 1
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 5 Register for Channel 1
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 6 Register for Channel 1
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 7 Register for Channel 1
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 0 Register for Channel 1
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 1 Register for Channel 1
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 2 Register for Channel 1
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 3 Register for Channel 1
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Source Address Register for Channel 1
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Destination Address Register for Channel 1
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Byte Count Register for Channel 1
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 0 Register for Channel 2
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 1 Register for Channel 2
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 2 Register for Channel 2
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 3 Register for Channel 2
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 4 Register for Channel 2
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 5 Register for Channel 2
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 6 Register for Channel 2
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 7 Register for Channel 2
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 0 Register for Channel 2
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 1 Register for Channel 2
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 2 Register for Channel 2
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 3 Register for Channel 2
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Source Address Register for Channel 2
address_offset : 0x168 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Destination Address Register for Channel 2
address_offset : 0x16C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Byte Count Register for Channel 2
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 0 Register for Channel 3
address_offset : 0x174 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 1 Register for Channel 3
address_offset : 0x178 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 2 Register for Channel 3
address_offset : 0x17C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 3 Register for Channel 3
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 4 Register for Channel 3
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 5 Register for Channel 3
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 6 Register for Channel 3
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 7 Register for Channel 3
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 0 Register for Channel 3
address_offset : 0x194 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 1 Register for Channel 3
address_offset : 0x198 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 2 Register for Channel 3
address_offset : 0x19C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 3 Register for Channel 3
address_offset : 0x1A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Source Address Register for Channel 3
address_offset : 0x1A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Destination Address Register for Channel 3
address_offset : 0x1A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Byte Count Register for Channel 3
address_offset : 0x1AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Engine Output Feedback Data After Cryptographic Operation
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Engine Output Feedback Data After Cryptographic Operation
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Control Register
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : AES Engine Start\nNote: This bit is always 0 when it's read back.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Start AES engine. BUSY flag will be set
End of enumeration elements list.
STOP : AES Engine Stop\nNote: This bit is always 0 when it's read back.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Stop AES engine
End of enumeration elements list.
KEYSZ : AES Key Size\nThis bit defines three different key size for AES operation.\nIf the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
bits : 2 - 3 (2 bit)
access : read-write
DMALAST : AES Last Block\nIn DMA mode, this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.\nThis bit is always 0 when it's read back. Must be written again once START is triggered.
bits : 5 - 5 (1 bit)
access : read-write
DMACSCAD : AES Engine DMA with Cascade Mode
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA cascade function Disabled
#1 : 1
In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation
End of enumeration elements list.
DMAEN : AES Engine DMA Enable Bit\nThe AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
AES DMA engine Disabled
#1 : 1
AES_DMA engine Enabled
End of enumeration elements list.
OPMODE : AES Engine Operation Modes
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
0x00 : 0
ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode)
0x02 : 2
CFB (Cipher Feedback Mode)
0x03 : 3
OFB (Output Feedback Mode)
0x04 : 4
CTR (Counter Mode)
0x10 : 16
CBC-CS1 (CBC Ciphertext-Stealing 1 Mode)
0x11 : 17
CBC-CS2 (CBC Ciphertext-Stealing 2 Mode)
0x12 : 18
CBC-CS3 (CBC Ciphertext-Stealing 3 Mode)
End of enumeration elements list.
ENCRYPTO : AES Encryption/Decryption
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
AES engine executes decryption operation
#1 : 1
AES engine executes encryption operation
End of enumeration elements list.
OUTSWAP : AES Engine Output Data Swap
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
INSWAP : AES Engine Input Data Swap
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
CHANNEL : AES Engine Working Channel
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Current control register setting is for channel 0
#01 : 1
Current control register setting is for channel 1
#10 : 2
Current control register setting is for channel 2
#11 : 3
Current control register setting is for channel 3
End of enumeration elements list.
KEYUNPRT : Unprotect Key\nWriting 0 to CRYPTO_AES_CTL[31] and '10110' to CRYPTO_AES_CTL[30:26] is to unprotect the AES key.\nThe KEYUNPRT can be read and written. When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
bits : 26 - 30 (5 bit)
access : read-write
KEYPRT : Protect Key\nRead as a flag to reflect KEYPRT.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Protect the content of the AES key from reading. The return value for reading CRYPTO_AESn_KEYx is not the content of the registers CRYPTO_AESn_KEYx. Once it is set, it can be cleared by asserting KEYUNPRT. And the key content would be cleared as well
End of enumeration elements list.
AES Engine Flag
address_offset : 0xB4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : AES Engine Busy
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
The AES engine is idle or finished
#1 : 1
The AES engine is under processing
End of enumeration elements list.
INBUFEMPTY : AES Input Buffer Empty
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
There are some data in input buffer waiting for the AES engine to process
#1 : 1
AES input buffer is empty. Software needs to feed data to the AES engine. Otherwise, the AES engine will be pending to wait for input data
End of enumeration elements list.
INBUFFULL : AES Input Buffer Full Flag
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
AES input buffer is not full. Software can feed the data into the AES engine
#1 : 1
AES input buffer is full. Software cannot feed data to the AES engine. Otherwise, the flag INBUFERR will be set to 1
End of enumeration elements list.
INBUFERR : AES Input Buffer Error Flag
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Error happens during feeding data to the AES engine
End of enumeration elements list.
CNTERR : CRYPTO_AESn_CNT Setting Error
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error in CRYPTO_AESn_CNT setting
#1 : 1
CRYPTO_AESn_CNT is 0 or not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode if DMAEN (CRYPTO_AES_CTL[7]) is enabled
End of enumeration elements list.
OUTBUFEMPTY : AES Out Buffer Empty
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
AES output buffer is not empty. There are some valid data kept in output buffer
#1 : 1
AES output buffer is empty. Software cannot get data from CRYPTO_AES_DATOUT. Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty
End of enumeration elements list.
OUTBUFFULL : AES Out Buffer Full Flag
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
AES output buffer is not full
#1 : 1
AES output buffer is full, and software needs to get data from CRYPTO_AES_DATOUT. Otherwise, the AES engine will be pending since the output buffer is full
End of enumeration elements list.
OUTBUFERR : AES Out Buffer Error Flag
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Error happens during getting the result from AES engine
End of enumeration elements list.
BUSERR : AES DMA Access Bus Error Flag
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Bus error will stop DMA operation and AES engine
End of enumeration elements list.
KSERR : AES Engine Access Key Store Error Flag
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Access error will stop AES engine
End of enumeration elements list.
AES Engine Data Input Port Register
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATIN : AES Engine Input Port\nCPU feeds data to AES engine through this port by checking CRYPTO_AES_STS. Feed data as INBUFFULL is 0.
bits : 0 - 31 (32 bit)
access : read-write
AES Engine Data Output Port Register
address_offset : 0xBC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATOUT : AES Engine Output Port\nCPU gets results from the AES engine through this port by checking CRYPTO_AES_STS. Get data as OUTBUFEMPTY is 0.
bits : 0 - 31 (32 bit)
access : read-only
AES Engine Output Feedback Data After Cryptographic Operation
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 0 Register for Channel 0
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. \n{CRYPTO_AESn_KEY3, CRYPTO_AESn_KEY2, CRYPTO_AESn_KEY1, CRYPTO_AESn_KEY0} stores the 128-bit security key for AES operation. \n{CRYPTO_AESn_KEY5, CRYPTO_AESn_KEY4, CRYPTO_AESn_KEY3, CRYPTO_AESn_KEY2, CRYPTO_AESn_KEY1, CRYPTO_AESn_KEY0} stores the 192-bit security key for AES operation. \n{CRYPTO_AESn_KEY7, CRYPTO_AESn_KEY6, CRYPTO_AESn_KEY5, CRYPTO_AESn_KEY4, CRYPTO_AESn_KEY3, CRYPTO_AESn_KEY2, CRYPTO_AESn_KEY1, CRYPTO_AESn_KEY0} stores the 256-bit security key for AES operation.
bits : 0 - 31 (32 bit)
access : read-write
AES Key Word 1 Register for Channel 0
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 2 Register for Channel 0
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 3 Register for Channel 0
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 4 Register for Channel 0
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 5 Register for Channel 0
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 6 Register for Channel 0
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 7 Register for Channel 0
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 0 Register for Channel 0
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV : AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0, CRYPTO_AESn_IV1, CRYPTO_AESn_IV2, and CRYPTO_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode. Four registers (CRYPTO_AESn_IV0, CRYPTO_AESn_IV1, CRYPTO_AESn_IV2, and CRYPTO_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
bits : 0 - 31 (32 bit)
access : read-write
AES Initial Vector Word 1 Register for Channel 0
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 2 Register for Channel 0
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 3 Register for Channel 0
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Control Register
address_offset : 0xEC0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
NUM : Read Key Number\nThe key number is sent to key store.
bits : 0 - 4 (5 bit)
access : write-only
RSRC : Read Key Destination
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
#0 : 0
Key is read from registers CRYPTO_AESx_KEYx
#1 : 1
Key is read from key store
End of enumeration elements list.
RSSRC : Read Key Store Destination
bits : 6 - 7 (2 bit)
access : write-only
Enumeration:
#00 : 0
Key is read from the SRAM of key store
#01 : 1
Key is read from the Flash of key store
#10 : 2
Key is read from the OTP of key store
End of enumeration elements list.
AES DMA Source Address Register for Channel 0
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (descryption) from SRAM memory space and do AES operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of SADDR are ignored.\nSADDR can be read and written. Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next AES operation.\nIn DMA mode, software can update the next CRYPTO_AESn_SADDR before triggering START.\nThe value of CRYPTO_AESn_SADDR and CRYPTO_AESn_DADDR can be the same.
bits : 0 - 31 (32 bit)
access : read-write
AES DMA Destination Address Register for Channel 0
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO. The DADDR keeps the destination address of the data buffer where the engine output's text will be stored. Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished. The start of destination address should be located at word boundary. In other words, bit 1 and 0 of DADDR are ignored.\nDADDR can be read and written. Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of DADDR will be updated later on. Consequently, software can prepare the destination address for the next AES operation.\nIn DMA mode, software can update the next CRYPTO_AESn_DADDR before triggering START. \nThe value of CRYPTO_AESn_SADDR and CRYPTO_AESn_DADDR can be the same.
bits : 0 - 31 (32 bit)
access : read-write
AES Byte Count Register for Channel 0
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : AES Byte Count\nThe CRYPTO_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode. The CRYPTO_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\nCRYPTO_AESn_CNT can be read and written. Writing to CRYPTO_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation. But the value of CRYPTO_AESn_CNT will be updated later on. Consequently, software can prepare the byte count of data for the next AES operation.\nAccording to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more than 16 bytes. Operations that are qual or less than one block will output unexpected result.\nIn Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRYPTO_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRYPTO_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
bits : 0 - 31 (32 bit)
access : read-write
AES Key Word 0 Register for Channel 1
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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