\n
address_offset : 0x0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x450 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
RSA Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : RSA Accelerator Start\nNote: This bit is always 0 when it is read back.\nRSA accelerator will ignore this START signal when BUSY flag is 1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Start RSA accelerator. BUSY flag will be set
End of enumeration elements list.
STOP : RSA Accelerator Stop\nNote: This bit is always 0 when it is read back.\nRemember to clear RSA interrupt flag after stopping RSA accelerator.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Abort RSA accelerator and make it into initial state
End of enumeration elements list.
CRT : CRT Enable Control\nNote: CRT is only used in decryption with key length 2048, 3072,4096 bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRT Disabled
#1 : 1
CRT Enabled
End of enumeration elements list.
CRTBYP : CRT Bypass Enable Control\nCRT bypass is only used in CRT decryption with the same key.\nNote: If users want to decrypt repeatedly with the same key, they can execute CRT bypass mode after the first time CRT decryption (means the second time to the latest time), but they cannot set CRTBYP to 1 in non-CRT mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRT Bypass Disabled
#1 : 1
CRT Bypass Enabled
End of enumeration elements list.
KEYLENG : The Key Length of RSA Operation
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
1024 bits
#01 : 1
2048 bits
#10 : 2
3072 bits
#11 : 3
4096 bits
End of enumeration elements list.
SCAP : Side Channel Attack Protection Enable Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Side Channel Attack Protection Disabled
#1 : 1
Side Channel Attack Protection Enabled
End of enumeration elements list.
BIST : Bistmode Enable Control\nNote: The Bistmode is used to enable the BIST operation if high enables the BIST controller to do embedded SRAM test.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bistmode Disabled
#1 : 1
Bistmode Enabled
End of enumeration elements list.
RSA DMA Source Address Register2
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR2 : RSA DMA Source Address Register2\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator.\nThis register stores the address of RSA the Exponent of Exponentiation (E).
bits : 0 - 31 (32 bit)
access : read-write
RSA DMA Source Address Register3
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR3 : RSA DMA Source Address Register3\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator.\nThis register stores the address of RSA the Factor of Modulus Operation (p).
bits : 0 - 31 (32 bit)
access : read-write
RSA DMA Source Address Register4
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR4 : RSA DMA Source Address Register4\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator.\nThis register stores the address of RSA the Factor of Modulus Operation (q).
bits : 0 - 31 (32 bit)
access : read-write
RSA DMA Destination Address Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : RSA DMA Destination Address Register\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator.\nThis register stores the address of RSA DMA Destination Address Register (Ans).
bits : 0 - 31 (32 bit)
access : read-write
RSA DMA Middle Address Register0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MADDR0 : RSA DMA Middle Address Register0\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator.\nThis register stores the address of RSA CRT the Temporary Value (Cp - Mp - Sp).
bits : 0 - 31 (32 bit)
access : read-write
RSA DMA Middle Address Register1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MADDR1 : RSA DMA Middle Address Register1\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator.\nThis register stores the address of RSA CRT the Temporary Value (Cq - Mq - Sq).
bits : 0 - 31 (32 bit)
access : read-write
RSA DMA Middle Address Register2
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MADDR2 : RSA DMA Middle Address Register2\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator.\nThis register stores the address of RSA CRT the Temporary Value (Dp).
bits : 0 - 31 (32 bit)
access : read-write
RSA DMA Middle Address Register3
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MADDR3 : RSA DMA Middle Address Register3\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator.\nThis register stores the address of RSA CRT the Temporary Value (Dq).
bits : 0 - 31 (32 bit)
access : read-write
RSA DMA Middle Address Register4
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MADDR4 : RSA DMA Middle Address Register4\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator.\nThis register stores the address of RSA CRT the Temporary Value (Rp).
bits : 0 - 31 (32 bit)
access : read-write
RSA DMA Middle Address Register5
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MADDR5 : RSA DMA Middle Address Register5\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator.\nThis register stores the address of RSA CRT the Temporary Value (Rq).
bits : 0 - 31 (32 bit)
access : read-write
RSA DMA Middle Address Register6
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MADDR6 : RSA DMA Middle Address Register6\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator.\nThis register stores the address of RSA SCA Protection the Temporary Value (E').
bits : 0 - 31 (32 bit)
access : read-write
RSA Status Register
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : RSA Accelerator Busy Flag\nNote: Remember to clear RSA interrupt flag after RSA accelerator is finished
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
The RSA accelerator is idle or finished
#1 : 1
The RSA accelerator is under processing and protects all registers
End of enumeration elements list.
DMABUSY : RSA DMA Busy Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
RSA DMA is idle or finished
#1 : 1
RSA DMA is busy
End of enumeration elements list.
BISTFA : Bist Fail Flag [RAM4~1]\nNote: The Bist Fail indicates if the BIST test fails or succeeds. If the Bist Fail is low at the end, the embedded SRAM pass the BIST test, otherwise, it is faulty. The BistFail will be high once the BIST detects the error and remains high during the BIST operation.
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : 0
No fail
1 : 1
Bistmode is failed
End of enumeration elements list.
BISTFIN : Bist Finish Flag [RAM4~1]\nNote: The Finish indicates the end of the BIST operation. When the BIST controller finishes all operations, this bit will be high.
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
0 : 0
Bistmode is on-going or unexecuted
1 : 1
Bistmode is finished
End of enumeration elements list.
BUSERR : RSA DMA Access Bus Error Flag
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Bus error will stop DMA operation and RSA accelerator
End of enumeration elements list.
CTLERR : RSA Control Register Error Flag\nNote: If the control error condition is used, but START(CRYPTO_RSA_CTL[0]) is not set to 1, CTLERR is still set to 1.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
RSA control error. RSA will not start in the unsupported situation
End of enumeration elements list.
KSERR : RSA Engine Access Key Store Error Flag
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Access error will stop RSA engine
End of enumeration elements list.
RSA Key Control Register
address_offset : 0x450 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
NUM : Read Key Number\nThe key number is sent to key store
bits : 0 - 4 (5 bit)
access : write-only
RSRC : Read Key Destination
bits : 5 - 5 (1 bit)
access : write-only
Enumeration:
#0 : 0
key is read from RSA engine
#1 : 1
key is read from key store
End of enumeration elements list.
RSSRC : Read Key Store Destination
bits : 6 - 7 (2 bit)
access : write-only
Enumeration:
#00 : 0
Key is read from the SRAM of key store
#01 : 1
Key is read from the Flash of key store
#10 : 2
Key is read from the OTP of key store
End of enumeration elements list.
BKNUM : Read Exponent Blind Key Number\nThe key number is sent to key store, and its destination always be the SRAM of key store. CPU cannot read the exponent blind key.\nNote: Use this key number only when executing SCA protection but no-CRT mode.
bits : 8 - 12 (5 bit)
access : write-only
RSA Key Status Register 0
address_offset : 0x454 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUM0 : Key Number0 (P)\nThe key number is generated by key store, and RSA can get complete p by key number in Key Store while operating.
bits : 0 - 4 (5 bit)
access : read-write
NUM1 : Key Number1 (Q)\nThe key number is generated by key store, and RSA can get complete q by key number in Key Store while operating.
bits : 8 - 12 (5 bit)
access : read-write
NUM2 : Key Number2 (Cp)\nThe key number is generated by key store, and RSA can get or store Cp by key number in Key Store while operating.
bits : 16 - 20 (5 bit)
access : read-write
NUM3 : Key Number3 (Cq)\nThe key number is generated by key store, and RSA can get or store Cq by key number in Key Store while operating.
bits : 24 - 28 (5 bit)
access : read-write
RSA Key Status Register 1
address_offset : 0x458 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUM4 : Key Number4 (Dp)\nThe key number is generated by key store, and RSA can get or store Dp by key number in Key Store while operating.
bits : 0 - 4 (5 bit)
access : read-write
NUM5 : Key Number5 (Dq)\nThe key number is generated by key store, and RSA can get or store Dq by key number in Key Store while operating.
bits : 8 - 12 (5 bit)
access : read-write
NUM6 : Key Number6 (Rp)\nThe key number is generated by key store, and RSA can get or store Rp by key number in Key Store while operating.
bits : 16 - 20 (5 bit)
access : read-write
NUM7 : Key Number7 (Rq)\nThe key number is generated by key store, and RSA can get or store Rq by key number in Key Store while operating.
bits : 24 - 28 (5 bit)
access : read-write
RSA DMA Source Address Register0
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR0 : RSA DMA Source Address Register0\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator.\nThis register stores the address of RSA the Base of Exponentiation (M).
bits : 0 - 31 (32 bit)
access : read-write
RSA DMA Source Address Register1
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR1 : RSA DMA Source Address Register1\nThe RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator.\nThis register stores the address of RSA the Base of Modulus Operation (N).
bits : 0 - 31 (32 bit)
access : read-write
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