SYST_CTRL

SYST_LOAD

SYST_VAL

ICSR

VTOR

AIRCR

SCR

CCR

SHPR2

SHPR3

SHCSR

ENABLE : System Tick Counter Enabled
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TICKINT : System Tick Interrupt Enabled
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKSRC : System Tick Clock Source Selection
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COUNTFLAG : System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
bits : 16 - 16 (1 bit)
access : read-write

RELOAD : System Tick Reload Value\nThe value to load into the Current Value register when the counter reaches 0.
bits : 0 - 23 (24 bit)
access : read-write

CURRENT : System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0.
bits : 0 - 23 (24 bit)
access : read-write

VECTACTIVE : Number of the Current Active Exception (Read Only)
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

End of enumeration elements list.

VECTPENDING : Number of the Highest Pended Exception (Read Only)
bits : 12 - 19 (8 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISRPENDING : Interrupt Pending Flag, Excluding NMI and Faults (Read Only)
bits : 22 - 22 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISRPREEMPT : Interrupt Preempt Bit (Read Only)\nIf set, a pending exception will be serviced on exit from the debug halt state.
bits : 23 - 23 (1 bit)
access : read-only

PENDSTCLR : SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDST bit, you must 'write 0 to PENDSTSET and write 1 to PENDSTCLR' at the same time.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PENDSTSET : SysTick Exception Set-pending Bit\nWrite Operation:
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PENDSVCLR : PendSV Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDSV bit, you must 'write 0 to PENDSVSET and write 1 to PENDSVCLR' at the same time.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PENDSVSET : PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NMIPENDCLR : NMI Bit-pending Bit\nNote: If AIRCR.BFHFNMINS is 0, this bit is RAZ/WI from Non-secure state.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NMIPENDSET : NMI Set-pending Bit\nWrite Operation:\nNote: If AIRCR.BFHFNMINS is 0, this bit is RAZ/WI from Non-secure state.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TBLOFF : Table Offset Bits\nThe vector table address for the selected Security state.
bits : 9 - 31 (23 bit)
access : read-write

VECTCLRACTIVE : Exception Active Status Clear Bit\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack.\nNote: This bit reads as zero.
bits : 1 - 1 (1 bit)
access : read-write

SYSRESETREQ : System Reset Request Bit\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence.
bits : 2 - 2 (1 bit)
access : read-write

SYSRESETREQS : System Reset Request Secure Only Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRIS : Priority Secure Exceptions Bit
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENDIANNESS : Data Endianness (Read Only)
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

VECTORKEY : Register Access Key\nWhen writing this register, this field should be 0x05FA, otherwise the write action will be ignored.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.
bits : 16 - 31 (16 bit)
access : read-write

SLEEPONEXIT : Sleep-on-exit Enable Control\nThis bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nNote: Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLEEPDEEP : Processor Deep Sleep and Sleep Mode Selection\nControl Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEVONPEND : Send Event on Pending\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRI_11 : Priority of System Handler 11 - SVCall\n'0' denotes the highest priority and '3' denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI_14 : Priority of System Handler 14 - PendSV\n'0' denotes the highest priority and '3' denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_15 : Priority of System Handler 15 - SysTick\n'0' denotes the highest priority and '3' denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

HARDFAULTPENDED : HardFault Exception Pended State \nThis bit indicates and allows modification of the pending state of\nthe HardFault exception corresponding to the selected Security state.\nThis bit is banked between Security states.\nThe possible values of this bit are:
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.