Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x180 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
IRQ0 ~ IRQ31 Set-enable Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER1 registers enable interrupts, and show which interrupts are enabled\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
IRQ0 ~ IRQ31 Set-pending Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR1 registers force interrupts into the pending state, and show which interrupts are pending\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Changes interrupt state to pending.\nInterrupt is pending
End of enumeration elements list.
IRQ32 ~ IRQ63 Set-pending Control Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR1 registers force interrupts into the pending state, and show which interrupts are pending\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Changes interrupt state to pending.\nInterrupt is pending
End of enumeration elements list.
IRQ0 ~ IRQ31 Clear-pending Control Register
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALPEND : Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR1 registers remove the pending state from interrupts, and show which interrupts are pending\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Removes pending state an interrupt.\nInterrupt is pending
End of enumeration elements list.
IRQ32 ~ IRQ63 Clear-pending Control Register
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALPEND : Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR1 registers remove the pending state from interrupts, and show which interrupts are pending\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Removes pending state an interrupt.\nInterrupt is pending
End of enumeration elements list.
IRQ0 ~ IRQ31 Active Bit Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR1 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
interrupt not active
1 : 1
interrupt active
End of enumeration elements list.
IRQ32 ~ IRQ63 Active Bit Register
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR1 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
interrupt not active
1 : 1
interrupt active
End of enumeration elements list.
IRQ32 ~ IRQ63 Set-enable Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER2 registers enable interrupts, and show which interrupts are enabled\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
IRQ0 ~ IRQ31 Clear-enable Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALENA : Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER1 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Disabled.\nInterrupt Enabled
End of enumeration elements list.
IRQ32 ~ IRQ63 Clear-enable Control Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALENA : Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER2 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Disabled.\nInterrupt Enabled
End of enumeration elements list.
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