Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x60 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xB4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x70 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x90 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTEN : HXT Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Reset by powr on reset.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~32 MHz external high speed crystal (HXT) Disabled
#1 : 1
4~32 MHz external high speed crystal (HXT) Enabled
End of enumeration elements list.
LXTEN : LXT Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Reset by RTC powr on reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
32.768 kHz external low speed crystal (LXT) Disabled
#1 : 1
32.768 kHz external low speed crystal (LXT) Enabled
End of enumeration elements list.
HIRCEN : HIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
48 MHz internal high speed RC oscillator (HIRC) Disabled
#1 : 1
48 MHz internal high speed RC oscillator (HIRC) Enabled
End of enumeration elements list.
LIRCEN : LIRC Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: LIRC will also be forced on when 1. Power down and ~(CONFIG0[3] CONFIG0[4] ~CONFIG0[31] CONFIG0[30]) 2. Not power down and ~(CONFIG0[3] CONFIG0[4] CONFIG0[31])
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
38.4 kHz internal low speed RC oscillator (LIRC) Disabled
#1 : 1
38.4 kHz internal low speed RC oscillator (LIRC) Enabled
End of enumeration elements list.
PDWKDLY : Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at 4~32 MHz external high speed crystal oscillator (HXT),\nThe delayed clock cycle is 512 clock cycles when chip works at 48 MHz internal high speed RC oscillator (HIRC)\nThe delayed clock cycle is 32 clock cycles when chip works at 4 MHz internal median speed RC oscillator (MIRC)\n\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock cycles delay Disabled
#1 : 1
Clock cycles delay Enabled
End of enumeration elements list.
PDWKIEN : Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PDWKIF and PDWKIEN are high.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power-down mode wake-up interrupt Disabled
#1 : 1
Power-down mode wake-up interrupt Enabled
End of enumeration elements list.
PDWKIF : Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event' indicates that resume from Power-down mode' \nThe flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.\nNote1: Write 1 to clear the bit to 0.\nNote2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) is set to 1.
bits : 6 - 6 (1 bit)
access : read-write
PDEN : System Power-down Enable (Write Protect)\nWhen this bit is set to 1, Power-down mode is enabled, chip enters Power-down mode immediately after the PDEN bit set. When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down.\nIn Power-down mode, HXT ,MIRC and HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode.\nIn Power-down mode, the PLL, HCLK, PCLK0 and PCLK1 clocks are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip operating normally or chip in idle mode because of WFI command
#1 : 1
Chip enters Power-down mode instant or wait CPU sleep command WFI
End of enumeration elements list.
MIRCEN : MIRC Enable Bit (Write Protect)
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
4 MHz internal high speed RC oscillator (MIRC) Disabled
#1 : 1
4 MHz internal high speed RC oscillator (MIRC) Enabled
End of enumeration elements list.
HXTGAIN : HXT Gain Control Bit (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nGain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off. \nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Reset by power on reset.
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
HXT frequency 1~4 MHz
#001 : 1
HXT frequency 4~8 MHz
#011 : 3
HXT frequency 12~ 16 MHz
#100 : 4
HXT frequency 16~24 MHz
#101 : 5
HXT frequency 24~32 Mhz
End of enumeration elements list.
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKSEL : HCLK Clock Source Selection (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turned on.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: Reset by power on reset.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HXT
#001 : 1
Clock source from LXT
#010 : 2
Clock source from PLL
#011 : 3
Clock source from LIRC
#101 : 5
Clock source from MIRC
#111 : 7
Clock source from HIRC
End of enumeration elements list.
STCLKSEL : Cortex-M23 SysTick Clock Source Selection (Write Protect)\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HXT
#001 : 1
Clock source from LXT
#010 : 2
Clock source from HXT/2
#011 : 3
Clock source from HCLK/2
#111 : 7
Clock source from HIRC/2
End of enumeration elements list.
USBDSEL : USB Device Clock Source Selection (Write Protect)\nThese bits are protected bit. It means programming this bit needs to write '59h', '16h', '88h' to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from HIRC
#1 : 1
Clock source from PLL Divided
End of enumeration elements list.
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTSEL : Watchdog Timer Clock Source Selection (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register. \nNote2: This bit is forced to 11 when CONFIG0[31] or CONFIG0[4] or CONFIG0[3] is 0.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved.
#01 : 1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#10 : 2
Clock source from HCLK/2048
#11 : 3
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
End of enumeration elements list.
WWDTSEL : Window Watchdog Timer Clock Source Selection (Write Protect)
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#10 : 2
Clock source from HCLK/2048
#11 : 3
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
End of enumeration elements list.
CLKOSEL : Clock Divider Clock Source Selection
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#001 : 1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010 : 2
Clock source from HCLK
#011 : 3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#101 : 5
Clock source from 4 MHz internal medium speed RC oscillator (MIRC)
#110 : 6
Clock source from PLL
#111 : 7
Clock source from USB SOF
End of enumeration elements list.
TMR0SEL : TIMER0 Clock Source Selection
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#001 : 1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK0
#011 : 3
Clock source from external clock T0 pin
#101 : 5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR1SEL : TIMER1 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#001 : 1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK0
#011 : 3
Clock source from external clock T1 pin
#101 : 5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR2SEL : TIMER2 Clock Source Selection
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#001 : 1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK1
#011 : 3
Clock source from external clock T2 pin
#101 : 5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
TMR3SEL : TIMER3 Clock Source Selection
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#001 : 1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK1
#011 : 3
Clock source from external clock T3 pin
#101 : 5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
UART0SEL : UART0 Clock Source Selection
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#001 : 1
Clock source from PLL
#010 : 2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#011 : 3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from PCLK0
#101 : 5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
End of enumeration elements list.
UART1SEL : UART1 Clock Source Selection
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#001 : 1
Clock source from PLL
#010 : 2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#011 : 3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from PCLK1
#101 : 5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
End of enumeration elements list.
Clock Source Select Control Register 2
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM0SEL : PWM0 Clock Source Selection\nThe peripheral clock source of PWM0 is defined by PWM0SEL.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL
#1 : 1
Clock source from PCLK0
End of enumeration elements list.
PWM1SEL : PWM1 Clock Source Selection\nThe peripheral clock source of PWM1 is defined by PWM1SEL.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL
#1 : 1
Clock source from PCLK1
End of enumeration elements list.
QSPI0SEL : QSPI0 Clock Source Selection
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK0
#11 : 3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
SPI0SEL : SPI0 Clock Source Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK1
#11 : 3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
BPWM0SEL : BPWM0 Clock Source Selection\nThe peripheral clock source of BPWM0 is defined by BPWM0SEL.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL
#1 : 1
Clock source from PCLK0
End of enumeration elements list.
BPWM1SEL : BPWM1 Clock Source Selection\nThe peripheral clock source of BPWM1 is defined by BPWM1SEL.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from PLL
#1 : 1
Clock source from PCLK1
End of enumeration elements list.
PSIOSEL : PSIO Clock Source Selection
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#001 : 1
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#010 : 2
Clock source from PCLK1
#011 : 3
Clock source from PLL
#100 : 4
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
#111 : 7
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
Clock Source Select Control Register 3
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SC0SEL : SC0 Clock Source Selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#01 : 1
Clock source from PLL
#10 : 2
Clock source from PCLK0
#11 : 3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
End of enumeration elements list.
UART2SEL : UART2 Clock Source Selection
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from 4~32 MHz external high speed crystal oscillator (HXT)
#001 : 1
Clock source from PLL
#010 : 2
Clock source from 32.768 kHz external low speed crystal oscillator (LXT)
#011 : 3
Clock source from 48 MHz internal high speed RC oscillator (HIRC)
#100 : 4
Clock source from PCLK0
#101 : 5
Clock source from 38.4 kHz internal low speed RC oscillator (LIRC)
End of enumeration elements list.
Clock Divider Number Register 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write
USBDIV : USB Clock Divide Number From PLL Clock
bits : 4 - 7 (4 bit)
access : read-write
UART0DIV : UART0 Clock Divide Number From UART0 Clock Source
bits : 8 - 11 (4 bit)
access : read-write
UART1DIV : UART1 Clock Divide Number From UART1 Clock Source
bits : 12 - 15 (4 bit)
access : read-write
EADCDIV : EADC Clock Divide Number From EADC Clock Source
bits : 16 - 23 (8 bit)
access : read-write
Clock Divider Number Register 1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SC0DIV : SC0 Clock Divide Number From SC0 Clock Source
bits : 0 - 7 (8 bit)
access : read-write
PSIODIV : PSIO Clock Divide Number From PSIO Clock Source
bits : 24 - 31 (8 bit)
access : read-write
Clock Divider Number Register 4
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART2DIV : UART2 Clock Divide Number From UART2 Clock Source
bits : 0 - 3 (4 bit)
access : read-write
APB Clock Divider Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APB0DIV : APB0 Clock DIvider\nAPB0 clock can be divided from HCLK\nOthers: Reserved.
bits : 0 - 2 (3 bit)
access : read-write
APB1DIV : APB1 Clock DIvider\nAPB1 clock can be divided from HCLK\nOthers: Reserved.
bits : 4 - 6 (3 bit)
access : read-write
AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMACKEN : PDMA Controller Clock Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA peripheral clock Disabled
#1 : 1
PDMA peripheral clock Enabled
End of enumeration elements list.
ISPCKEN : Flash ISP Controller Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash ISP peripheral clock Disabled
#1 : 1
Flash ISP peripheral clock Enabled
End of enumeration elements list.
EBICKEN : EBI Controller Clock Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI peripheral clock Disabled
#1 : 1
EBI peripheral clock Enabled
End of enumeration elements list.
CRCCKEN : CRC Generator Controller Clock Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRC peripheral clock Disabled
#1 : 1
CRC peripheral clock Enabled
End of enumeration elements list.
CRYPTCKEN : Cryptographic Accelerator Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Cryptographic Accelerator clock Disabled
#1 : 1
Cryptographic Accelerator clock Enabled
End of enumeration elements list.
FMCIDLE : Flash Memory Controller Clock Enable Bit in IDLE Mode
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
FMC clock Disabled when chip is under IDLE mode,in this case, PDMA can not access FMC memory
#1 : 1
FMC clock Enabled when chip is under IDLE mode,PDMA can access FMC memory
End of enumeration elements list.
PLL Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBDIV : PLL Feedback Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 5 (6 bit)
access : read-write
INDIV : PLL Input Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 12 (4 bit)
access : read-write
OUTDIV : PLL Output Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 15 (2 bit)
access : read-write
PD : Power-down Mode (Write Protect)\nIf set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in normal mode
#1 : 1
PLL is in Power-down mode (default)
End of enumeration elements list.
BP : PLL Bypass Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL is in normal mode (default)
#1 : 1
PLL clock output is same as PLL input clock FIN
End of enumeration elements list.
OE : PLL OE (FOUT Enable) Pin Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL FOUT Enabled
#1 : 1
PLL FOUT is fixed low
End of enumeration elements list.
PLLSRC : PLL Source Clock Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote: MIRC and HIRC have to be both on when source switch between them
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#00 : 0
PLL source clock from 4~32 MHz external high-speed crystal oscillator (HXT)
#01 : 1
PLL source clock from 12 MHz internal high-speed oscillator (HIRC/4)
#10 : 2
PLL source clock from 4~32 MHz external high-speed crystal oscillator (HXT)
#11 : 3
PLL source clock from 4 MHz internal high-speed oscillator (MIRC)
End of enumeration elements list.
STBSEL : PLL Stable Counter Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
PLL stable time is 1200 PLL source clock (suitable for source clock is equal to or less than 12 MHz)
#1 : 1
PLL stable time is 3200 PLL source clock (suitable for source clock is larger than 12 MHz)
End of enumeration elements list.
PLL_CLF_EN : 1: PLL Clock Filter On\n0 : OFF
bits : 24 - 24 (1 bit)
access : read-write
Clock Status Monitor Register
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HXTSTB : HXT Clock Source Stable Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
4~32 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled
#1 : 1
4~32 MHz external high speed crystal oscillator (HXT) clock is stable and enabled
End of enumeration elements list.
LXTSTB : LXT Clock Source Stable Flag (Read Only)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled
#1 : 1
32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled
End of enumeration elements list.
PLLSTB : Internal PLL Clock Source Stable Flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal PLL clock is not stable or disabled
#1 : 1
Internal PLL clock is stable and enabled
End of enumeration elements list.
LIRCSTB : LIRC Clock Source Stable Flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
38.4 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled
#1 : 1
38.4 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled
End of enumeration elements list.
HIRCSTB : HIRC Clock Source Stable Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
48 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled
#1 : 1
48 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled
End of enumeration elements list.
MIRCSTB : MIRC Clock Source Stable Flag (Read Only)
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
4 MHz internal mid speed RC oscillator (MIRC) clock is not stable or disabled
#1 : 1
4 MHz internal mid speed RC oscillator (MIRC) clock is stable and enabled
End of enumeration elements list.
CLKSFAIL : Clock Switching Fail Flag \nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote: Write 1 to clear the bit to 0.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clock switching success
#1 : 1
Clock switching failure
End of enumeration elements list.
Clock Output Control Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write
CLKOEN : Clock Output Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Output function Disabled
#1 : 1
Clock Output function Enabled
End of enumeration elements list.
DIV1EN : Clock Output Divide One Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock Output will output clock with source frequency divided by FREQSEL
#1 : 1
Clock Output will output clock with source frequency
End of enumeration elements list.
CLK1HZEN : Clock Output 1Hz Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
1 Hz clock output for 32.768 kHz frequency compensation Disabled
#1 : 1
1 Hz clock output for 32.768 kHz frequency compensation Enabled
End of enumeration elements list.
Clock Fail Detector Control Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFDEN : HXT Clock Fail Detector Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~32 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled
#1 : 1
4~32 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled
End of enumeration elements list.
HXTFIEN : HXT Clock Fail Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled
#1 : 1
4~32 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled
End of enumeration elements list.
LXTFDEN : LXT Clock Fail Detector Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled
#1 : 1
32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled
End of enumeration elements list.
LXTFIEN : LXT Clock Fail Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled
#1 : 1
32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled
End of enumeration elements list.
HXTFQDEN : HXT Clock Frequency Range Detector Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled
#1 : 1
4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled
End of enumeration elements list.
HXTFQIEN : HXT Clock Frequency Range Detector Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled
#1 : 1
4~32 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled
End of enumeration elements list.
Clock Fail Detector Status Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFIF : HXT Clock Fail Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~32 MHz external high speed crystal oscillator (HXT) clock is normal
#1 : 1
4~32 MHz external high speed crystal oscillator (HXT) clock stops
End of enumeration elements list.
LXTFIF : LXT Clock Fail Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
32.768 kHz external low speed crystal oscillator (LXT) clock is normal
#1 : 1
32.768 kHz external low speed crystal oscillator (LXT) stops
End of enumeration elements list.
HXTFQIF : HXT Clock Frequency Range Detector Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
4~32 MHz external high speed crystal oscillator (HXT) clock frequency is normal
#1 : 1
4~32 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal
End of enumeration elements list.
Clock Frequency Range Detector Upper Boundary Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UPERBD : HXT Clock Frequency Range Detector Upper Boundary Value\nThe bits define the maximum value of frequency range detector window.\nWhen HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.\nNote :Frequency out of range will be asserted when HIRC_period*1024 HXT_period*CLK_DUPB or HIRC_period*1024 HXT_period*CLK_CDLOWB.
bits : 0 - 9 (10 bit)
access : read-write
Clock Frequency Range Detector Lower Boundary Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOWERBD : HXT Clock Frequency Range Detector Lower Boundary Value\nThe bits define the minimum value of frequency range detector window.\nWhen HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.\nNote :The frequency out of range will be asserted when HIRC_period*1024 HXT_period*CLK_DUPB or HIRC_period*1024 HXT_period*CLK_CDLOWB.
bits : 0 - 9 (10 bit)
access : read-write
APB Devices Clock Enable Control Register 0
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTCKEN : Watchdog Timer Clock Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This bit is forced to 1 when CONFIG0[3] or CONFIG0[4] or CONFIG0[31] is 0.\nNote3: Reset by power on reset or watch dog reset or software chip reset.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog timer clock Disabled
#1 : 1
Watchdog timer clock Enabled
End of enumeration elements list.
RTCCKEN : Real-time-clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only. The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]). It can be selected to 32.768 kHz external low speed crystal or 38.4 kHz internal low speed RC oscillator (LIRC).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC clock Disabled
#1 : 1
RTC clock Enabled
End of enumeration elements list.
TMR0CKEN : Timer0 Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 clock Disabled
#1 : 1
Timer0 clock Enabled
End of enumeration elements list.
TMR1CKEN : Timer1 Clock Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 clock Disabled
#1 : 1
Timer1 clock Enabled
End of enumeration elements list.
TMR2CKEN : Timer2 Clock Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 clock Disabled
#1 : 1
Timer2 clock Enabled
End of enumeration elements list.
TMR3CKEN : Timer3 Clock Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 clock Disabled
#1 : 1
Timer3 clock Enabled
End of enumeration elements list.
CLKOCKEN : CLKO Clock Enable Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
CLKO clock Disabled
#1 : 1
CLKO clock Enabled
End of enumeration elements list.
ACMP01CKEN : Analog Comparator 0/1 Clock Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog comparator 0/1 clock Disabled
#1 : 1
Analog comparator 0/1 clock Enabled
End of enumeration elements list.
I2C0CKEN : I2C0 Clock Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0 clock Disabled
#1 : 1
I2C0 clock Enabled
End of enumeration elements list.
I2C1CKEN : I2C1 Clock Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C1 clock Disabled
#1 : 1
I2C1 clock Enabled
End of enumeration elements list.
QSPI0CKEN : QSPI0 Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
QSPI0 clock Disabled
#1 : 1
QSPI0 clock Enabled
End of enumeration elements list.
SPI0CKEN : SPI0 Clock Enable Bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 clock Disabled
#1 : 1
SPI0 clock Enabled
End of enumeration elements list.
UART0CKEN : UART0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 clock Disabled
#1 : 1
UART0 clock Enabled
End of enumeration elements list.
UART1CKEN : UART1 Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 clock Disabled
#1 : 1
UART1 clock Enabled
End of enumeration elements list.
UART2CKEN : UART2 Clock Enable Bit
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART2 clock Disabled
#1 : 1
UART2 clock Enabled
End of enumeration elements list.
USBDCKEN : USB Device Clock Enable Bit
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB Device clock Disabled
#1 : 1
USB Device clock Enabled
End of enumeration elements list.
EADCCKEN : Enhanced Analog-digital-converter (EADC) Clock Enable Bit
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADC clock Disabled
#1 : 1
EADC clock Enabled
End of enumeration elements list.
Power Manager Control Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMSEL : Power-down Mode Selection (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nThese bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Power-down mode is selected. (PD)
#010 : 2
fast wake up
#110 : 6
Deep Power-down mode is selected (DPD)
End of enumeration elements list.
WKTMREN : Wake-up Timer Enable (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up timer disable at DPD mode
#1 : 1
Wake-up timer enabled at DPD mode
End of enumeration elements list.
WKTMRIS : Wake-up Timer Time-out Interval Select (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nThese bits control wake-up timer time-out interval when chip at DPD mode.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#000 : 0
Time-out interval is 128 LIRC clocks (~3.368 ms)
#001 : 1
Time-out interval is 256 LIRC clocks (~6.736 ms)
#010 : 2
Time-out interval is 512 LIRC clocks (~13.47 ms)
#011 : 3
Time-out interval is 1024 LIRC clocks (~26.95 ms)
#100 : 4
Time-out interval is 4096 LIRC clocks (~107.79 ms)
#101 : 5
Time-out interval is 8192 LIRC clocks (~215.58 ms)
#110 : 6
Time-out interval is 16384 LIRC clocks (~431.16 ms)
#111 : 7
Time-out interval is 32768 LIRC clocks (~862.32 ms)
End of enumeration elements list.
WKPINEN0 : Wake-up Pin Enable 0 (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nThis is control register for PC.0 to wake-up pin.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Wake-up pin disable at Deep Power-down mode
#01 : 1
Wake-up pin rising edge enabled at Deep Power-down mode
#10 : 2
Wake-up pin falling edge enabled at Deep Power-down mode
#11 : 3
Wake-up pin both edge enabled at Deep Power-down mode
End of enumeration elements list.
WKPINDBEN : Wake-up Pin De-bounce Enable Bit (Write Protect)\nThe WKPINDBEN bit is used to enable the de-bounce function for wake-up pin. If the input signal pulse width cannot be sampled by continuous eight de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. The de-bounce clock source is the 38 kHz internal low speed RC oscillator (LIRC).\nThe de-bounce function is valid only for edge triggered.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Deep power-down wake-up pin De-bounce function disable
#1 : 1
Deep power-down wake-up pin De-bounce function enable
End of enumeration elements list.
RTCWKEN : RTC Wake-up Enable (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC wake-up disable at Deep Power-down mode or Standby Power-down mode
#1 : 1
RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode
End of enumeration elements list.
WKPINEN1 : Wake-up Pin Enable 1 (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nThis is control register for PB.0 to wake-up pin.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Wake-up pin disable at Deep Power-down mode
#01 : 1
Wake-up pin rising edge enabled at Deep Power-down mode
#10 : 2
Wake-up pin falling edge enabled at Deep Power-down mode
#11 : 3
Wake-up pin both edge enabled at Deep Power-down mode
End of enumeration elements list.
WKPINEN2 : Wake-up Pin Enable 2 (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nThis is control register for PB.2 to wake-up pin.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Wake-up pin disable at Deep Power-down mode
#01 : 1
Wake-up pin rising edge enabled at Deep Power-down mode
#10 : 2
Wake-up pin falling edge enabled at Deep Power-down mode
#11 : 3
Wake-up pin both edge enabled at Deep Power-down mode
End of enumeration elements list.
WKPINEN3 : Wake-up Pin Enable 3 (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nThis is control register for PB.12 to wake-up pin.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Wake-up pin disable at Deep Power-down mode
#01 : 1
Wake-up pin rising edge enabled at Deep Power-down mode
#10 : 2
Wake-up pin falling edge enabled at Deep Power-down mode
#11 : 3
Wake-up pin both edge enabled at Deep Power-down mode
End of enumeration elements list.
WKPINEN4 : Wake-up Pin Enable 4 (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nThis is control register for PF.6 to wake-up pin.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
Wake-up pin disable at Deep Power-down mode
#01 : 1
Wake-up pin rising edge enabled at Deep Power-down mode
#10 : 2
Wake-up pin falling edge enabled at Deep Power-down mode
#11 : 3
Wake-up pin both edge enabled at Deep Power-down mode
End of enumeration elements list.
Power Manager Status Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PINWK0 : Pin Wake-up 0 Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0). This flag is cleared when DPD mode is entered.
bits : 0 - 0 (1 bit)
access : read-only
TMRWK : Timer Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by wakeup timer time-out. This flag is cleared when DPD mode is entered.
bits : 1 - 1 (1 bit)
access : read-only
RTCWK : RTC Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Deep Power-down mode (DPD) was requested with a RTC alarm, tick time or tamper happened. This flag is cleared when DPD mode is entered.
bits : 2 - 2 (1 bit)
access : read-only
PINWK1 : Pin Wake-up 1 Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPB.0). This flag is cleared when DPD mode is entered.
bits : 3 - 3 (1 bit)
access : read-only
PINWK2 : Pin Wake-up 2 Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPB.2). This flag is cleared when DPD mode is entered.
bits : 4 - 4 (1 bit)
access : read-only
PINWK3 : Pin Wake-up 3 Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPB.12). This flag is cleared when DPD mode is entered.
bits : 5 - 5 (1 bit)
access : read-only
PINWK4 : Pin Wake-up 4 Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPF.6). This flag is cleared when DPD mode is entered.
bits : 6 - 6 (1 bit)
access : read-only
LVRWK : LVR Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Deep Power-down mode was requested with a LVR happened. This flag is cleared when DPD mode is entered.
bits : 12 - 12 (1 bit)
access : read-only
CLRWK : Clear Wake-up Flag\nNote: Reset by powr on reset.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not cleared
#1 : 1
Clear all wake-up flag
End of enumeration elements list.
HXT Filter Select Control Register
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HXTFSEL : HXT Filter Select \nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: This bit should not be changed during HXT running.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
HXT frequency is greater than 12 MHz
#1 : 1
HXT frequency is less than or equal to 12 MHz
End of enumeration elements list.
APB Devices Clock Enable Control Register 1
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SC0CKEN : SC0 Clock Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC0 clock Disabled
#1 : 1
SC0 clock Enabled
End of enumeration elements list.
USCI0CKEN : USCI0 Clock Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI0 clock Disabled
#1 : 1
USCI0 clock Enabled
End of enumeration elements list.
USCI1CKEN : USCI1 Clock Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI1 clock Disabled
#1 : 1
USCI1 clock Enabled
End of enumeration elements list.
USCI2CKEN : USCI2 Clock Enable Bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI1 clock Disabled
#1 : 1
USCI1 clock Enabled
End of enumeration elements list.
DACCKEN : DAC Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC clock Disabled
#1 : 1
DAC clock Enabled
End of enumeration elements list.
PWM0CKEN : PWM0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0 clock Disabled
#1 : 1
PWM0 clock Enabled
End of enumeration elements list.
PWM1CKEN : PWM1 Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1 clock Disabled
#1 : 1
PWM1 clock Enabled
End of enumeration elements list.
BPWM0CKEN : BPWM0 Clock Enable Bit
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0 clock Disabled
#1 : 1
BPWM0 clock Enabled
End of enumeration elements list.
BPWM1CKEN : BPWM1 Clock Enable Bit
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM1 clock Disabled
#1 : 1
BPWM1 clock Enabled
End of enumeration elements list.
OPACKEN : OP Amplifier (OPA) Clock Enable Bit
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OPA clock Disabled
#1 : 1
OPA clock Enabled
End of enumeration elements list.
PSIOCKEN : PSIO Clock Enable Bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
PSIO clock Disabled
#1 : 1
PSIO clock Enabled
End of enumeration elements list.
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