FMC_ISPCTL (ISPCTL)

FMC_ISPTRG (ISPTRG)

FMC_ISPADDR (ISPADDR)

FMC_ISPSTS (ISPSTS)

FMC_CYCCTL (CYCCTL)

FMC_KPKEY0 (KPKEY0)

FMC_KPKEY1 (KPKEY1)

FMC_KPKEY2 (KPKEY2)

FMC_KPKEYTRG (KPKEYTRG)

FMC_KPKEYSTS (KPKEYSTS)

FMC_KPKEYCNT (KPKEYCNT)

FMC_KPCNT (KPCNT)

FMC_ISPDAT (ISPDAT)

FMC_MPDAT0 (MPDAT0)

FMC_MPDAT1 (MPDAT1)

FMC_MPDAT2 (MPDAT2)

FMC_MPDAT3 (MPDAT3)

FMC_ISPCMD (ISPCMD)

FMC_MPSTS (MPSTS)

FMC_MPADDR (MPADDR)

FMC_XOMR0STS (XOMR0STS)

FMC_XOMR1STS (XOMR1STS)

FMC_XOMR2STS (XOMR2STS)

FMC_XOMR3STS (XOMR3STS)

FMC_XOMSTS (XOMSTS)

ISPEN : ISP Enable Bit (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BS : Boot Select (Write Protect) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

APUEN : APROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGUEN : CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDUEN : LDROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands\n(8) KPROM is erased/programmed if KEYLOCK is set to 1\n(9) APROM is erased/programmed if KEYLOCK is set to 1\n(10) LDROM is erased/programmed if KEYLOCK is set to 1\n(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0 \n(12) The address of block erase and bank erase is not in APROM\n(13) ISP CMD in XOM region, except mass erase, page erase and chksum command\n(14) The wrong setting of page erase ISP CMD in XOM\n(15) Violate XOM setting one time protection \n(16) Mass erase when MERASE (CFG0[13]) is disable\n(17) Page erase, mass erase , multi-word program or 64-bit word program in OTP\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

INTEN : ISP INT Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register. Before using INT, user needs to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPGO : ISP Start Trigger (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPADDR : ISP Address\nThe M261/M262/M263 series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.\nFor CRC32 Checksum Calculation command, this field is the Flash starting address for checksum calculation, 2 Kbytes alignment is necessary for CRC32 checksum calculation.\nFor Flash32-bit Program, ISP address needs word alignment (4-byte). For Flash 64-bit Program, ISP address needs double word alignment (8-byte).
bits : 0 - 31 (32 bit)
access : read-write

ISPBUSY : ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CBS : Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FCYCDIS : Flash Access Cycle Auto-tuning Disable Flag (Read Only)\nThis bit is set if Flash access cycle auto-tunning function is disabled. The auto-tunning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PGFF : Flash Program with Fast Verification Flag (Read Only)\nThis bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP Flash erase or ISP read CID operation
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands\n(8) KPROM is erased/programmed if KEYLOCK is set to 1\n(9) APROM is erased/programmed if KEYLOCK is set to 1\n(10) LDROM is erased/programmed if KEYLOCK is set to 1\n(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0.\n(12) The address of block erase and bank erase is not in APROM\n(13) ISP CMD in XOM region, except mass erase, page erase and chksum command\n(14) The wrong setting of page erase ISP CMD in XOM\n(15) Violate XOM setting one time protection \n(16) Mass erase when MERASE (CFG0[13]) is disable\n(17) Page erase, mass erase , multi-word program or 64-bit word program in OTP\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

ALLONE : Flash All-one Verification Flag This bit is set by hardware if all of Flash bits are 1, and clear if Flash bits are not all 1 after 'Run Flash All-One Verification' complete this bit also can be clear by writing 1
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECMAP : Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}
bits : 9 - 23 (15 bit)
access : read-only

INTFLAG : None
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CYCLE : Flash Access Cycle Control (Write Protect) This register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1).When auto-tuning function disabled, user needs to check the speed of HCLK and set the cycle 0. The optimized HCLK working frequency range is 49~79 MHz Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FADIS : Flash Access Cycle Auto-tuning Disable Bit (Write Protect)\nSet this bit to disable Flash access cycle auto-tuning function\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.When FMC is doing auto-tuning,we considered as a ISP operation need to monitor busy flag.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

KPKEY0 : KPROM KEY0 Data (Write Only)\nWrite KPKEY0 data to this register before KEY Comparison operation.
bits : 0 - 31 (32 bit)
access : write-only

KPKEY1 : KPROM KEY1 Data (Write Only)\nWrite KPKEY1 data to this register before KEY Comparison operation.
bits : 0 - 31 (32 bit)
access : write-only

KPKEY2 : KPROM KEY2 Data (Write Only)\nWrite KPKEY2 data to this register before KEY Comparison operation.
bits : 0 - 31 (32 bit)
access : write-only

KPKEYGO : KPROM KEY Comparison Start Trigger (Write Protect)\nWrite 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished. This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0.\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCEN : Timeout Counting Enable Bit (Write Protect)\n10 minutes is at least for timeout, and average is about 20 minutes.\nNote: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

KEYBUSY : KEY Comparison Busy (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

KEYLOCK : KEY LOCK Flag \nThis bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection. After Mass Erase operation, users must reset or power on /off to clear this bit to 0. This bit also can be set to 1 while:\nCPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or\nKEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or\nKEYENROM is programmed a non-0xFF value or\nTimeout event or\nFORBID(FMC_KPKEYSTS[3]) is 1\nCONFIG write protect is dependent on CFGFLAG.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

KEYMATCH : KEY Match Flag (Read Only) This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM and cleared to 0 if KEYs are unmatched. This bit is also cleared to 0 while CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or Timeout event or KPROM is erased or KEYENROM is programmed to a non-0xFF value. Chip is in Power-down mode.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FORBID : KEY Comparison Forbidden Flag (Read Only)\nThis bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]).
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

KEYFLAG : KEY Protection Enable Flag (Read Only)\nThis bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset. This bit is cleared to 0 by hardware while KPROM is erased. This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CFGFLAG : CONFIG Write-protection Enable Flag (Read Only)\nThis bit is set while the KEYENROM [0] is 0 at power-on or reset. This bit is cleared to 0 by hardware while KPROM is erased. This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

KPKECNT : Error Key Entry Counter at Each Power-on (Read Only)\nKPKECNT is increased when entry keys is wrong in Security Key protection. KPKECNT is cleared to 0 if key comparison is matched or system power-on.
bits : 0 - 5 (6 bit)
access : read-only

KPKEMAX : Maximum Number for Error Key Entry at Each Power-on (Read Only)\nKPKEMAX is the maximum error key entry number at each power-on. When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated. KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting. The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX.
bits : 8 - 13 (6 bit)
access : read-only

KPCNT : Power-on Counter for Error Key Entry (Read Only)\nKPCNT is the power-on counting for error key entry in Security Key protection. KPCNT is cleared to 0 if key comparison is matched.
bits : 0 - 3 (4 bit)
access : read-only

KPMAX : Power-on Maximum Number for Error Key Entry (Read Only)\nKPMAX is the power-on maximum number for error key entry. When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated. KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting. The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX
bits : 8 - 11 (4 bit)
access : read-only

ISPDAT : ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT0 : ISP Data 0\nThis register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT1 : ISP Data 1\nThis register is the second 32-bit data for 64-bit/multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT2 : ISP Data 2\nThis register is the third 32-bit data for multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT3 : ISP Data 3\nThis register is the fourth 32-bit data for multi-word programming.
bits : 0 - 31 (32 bit)
access : read-write

CMD : ISP Command\nISP command table is shown below:\nThe other commands are invalid.
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MPBUSY : ISP Multi-word Program Busy Flag (Read Only)\nWrite 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PPGO : ISP Multi-program Status (Read Only)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Read Only)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands.\n(8) KPROM is erased/programmed if KEYLOCK is set to 1\n(9) APROM is erased/programmed if KEYLOCK is set to 1\n(10) LDROM is erased/programmed if KEYLOCK is set to 1\n(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0.\n(12) The address of block erase and bank erase is not in APROM\n(13) ISP CMD in XOM region, except mass erase, page erase and chksum command\n(14) The wrong setting of page erase ISP CMD in XOM\n(15) Violate XOM setting one time protection \n(16) Mass erase when MERASE (CFG0[13]) is disable\n(17) Page erase, mass erase , multi-word program or 64-bit word program in OTP
bits : 2 - 2 (1 bit)
access : read-only

D0 : ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to Flash complete.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

D1 : ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to Flash complete.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

D2 : ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to Flash complete.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

D3 : ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to Flash complete.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MPADDR : ISP Multi-word Program Address\nMPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.\nMPADDR will keep the final ISP address when ISP multi-word program is complete.
bits : 0 - 31 (32 bit)
access : read-only

SIZE : XOM Region 0 Size (Page-aligned)\nSIZE is the page number of XOM Region 0.
bits : 0 - 7 (8 bit)
access : read-only

BASE : XOM Region 0 Base Address (Page-aligned)\nBASE is the base address of XOM Region 0.
bits : 8 - 31 (24 bit)
access : read-only

SIZE : XOM Region 1 Size (Page-aligned)\nSIZE is the page number of XOM Region 1.
bits : 0 - 7 (8 bit)
access : read-only

BASE : XOM Region 1 Base Address (Page-aligned)\nBASE is the base address of XOM Region 1.
bits : 8 - 31 (24 bit)
access : read-only

SIZE : XOM Region 2 Size (Page-aligned)\nSIZE is the page number of XOM Region 2.
bits : 0 - 7 (8 bit)
access : read-only

BASE : XOM Region 2 Base Address (Page-aligned)\nBASE is the base address of XOM Region 2.
bits : 8 - 31 (24 bit)
access : read-only

SIZE : XOM Region 3 Size (Page-aligned)\nSIZE is the page number of XOM Region 3.
bits : 0 - 7 (8 bit)
access : read-only

BASE : XOM Region 3 Base Address (Page-aligned)\nBASE is the base address of XOM Region 3.
bits : 8 - 31 (24 bit)
access : read-only

XOMR0ON : XOM Region 0 On\nXOM Region 0 active status.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

XOMR1ON : XOM Region 1 On\nXOM Region 1 active status.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

XOMR2ON : XOM Region 2 On\nXOM Region 2 active status.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

XOMR3ON : XOM Region 3 On\nXOM Region 3 active status.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

XOMPEF : XOM Page Erase Function Fail\nXOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.