\n

PDMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x80 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x90 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xA0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xB0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x60 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x70 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PDMA_DSCT0_NEXT

PDMA_DSCT1_NEXT

PDMA_DSCT2_NEXT

PDMA_DSCT3_NEXT

PDMA_DSCT4_NEXT

PDMA_DSCT5_NEXT

PDMA_DSCT6_NEXT

PDMA_DSCT7_NEXT

PDMA_DSCT8_NEXT

PDMA_DSCT9_NEXT

PDMA_DSCT10_NEXT

PDMA_DSCT11_NEXT


PDMA_DSCT0_NEXT

First Scatter-gather Descriptor Table Offset Address of PDMA Channel n\n(M45xD/M45xC Only Support Channel 0~7)
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT0_NEXT PDMA_DSCT0_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NEXT

NEXT : PDMA Next Descriptor Table Offset Address Register\nThis field indicates the offset of next descriptor table address in system memory. The system memory based address is 0x2000_0000 (PDMA_SCATBA), if the next descriptor table is 0x2000_0100, then this field must fill in 0x0100.\nNote1: The next descriptor table address must be word boundary.\nNote2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.
bits : 2 - 15 (14 bit)
access : read-write


PDMA_DSCT1_NEXT

First Scatter-gather Descriptor Table Offset Address of PDMA Channel n\n(M45xD/M45xC Only Support Channel 0~7)
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT1_NEXT PDMA_DSCT1_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT2_NEXT

First Scatter-gather Descriptor Table Offset Address of PDMA Channel n\n(M45xD/M45xC Only Support Channel 0~7)
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT2_NEXT PDMA_DSCT2_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT3_NEXT

First Scatter-gather Descriptor Table Offset Address of PDMA Channel n\n(M45xD/M45xC Only Support Channel 0~7)
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT3_NEXT PDMA_DSCT3_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT4_NEXT

First Scatter-gather Descriptor Table Offset Address of PDMA Channel n\n(M45xD/M45xC Only Support Channel 0~7)
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT4_NEXT PDMA_DSCT4_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT5_NEXT

First Scatter-gather Descriptor Table Offset Address of PDMA Channel n\n(M45xD/M45xC Only Support Channel 0~7)
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT5_NEXT PDMA_DSCT5_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT6_NEXT

First Scatter-gather Descriptor Table Offset Address of PDMA Channel n\n(M45xD/M45xC Only Support Channel 0~7)
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT6_NEXT PDMA_DSCT6_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT7_NEXT

First Scatter-gather Descriptor Table Offset Address of PDMA Channel n\n(M45xD/M45xC Only Support Channel 0~7)
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT7_NEXT PDMA_DSCT7_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT8_NEXT

First Scatter-gather Descriptor Table Offset Address of PDMA Channel n\n(M45xD/M45xC Only Support Channel 0~7)
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT8_NEXT PDMA_DSCT8_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT9_NEXT

First Scatter-gather Descriptor Table Offset Address of PDMA Channel n\n(M45xD/M45xC Only Support Channel 0~7)
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT9_NEXT PDMA_DSCT9_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT10_NEXT

First Scatter-gather Descriptor Table Offset Address of PDMA Channel n\n(M45xD/M45xC Only Support Channel 0~7)
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT10_NEXT PDMA_DSCT10_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT11_NEXT

First Scatter-gather Descriptor Table Offset Address of PDMA Channel n\n(M45xD/M45xC Only Support Channel 0~7)
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT11_NEXT PDMA_DSCT11_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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