Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
DAC Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACEN : DAC Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC is Disabled
#1 : 1
DAC is Enabled
End of enumeration elements list.
DACIEN : DAC Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt is Disabled
#1 : 1
Interrupt is Enabled
End of enumeration elements list.
DMAEN : DMA Mode Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA mode Disabled
#1 : 1
DMA mode Enabled
End of enumeration elements list.
DMAURIEN : DMA Under-run Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA underrun interrupt Disabled
#1 : 1
DMA underrun interrupt Enabled
End of enumeration elements list.
TRGEN : Trigger Mode Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC event trigger mode Disabled
#1 : 1
DAC event trigger mode Enabled
End of enumeration elements list.
TRGSEL : Trigger Source Selection
bits : 5 - 7 (3 bit)
access : read-write
Enumeration:
#000 : 0
Software trigger
#001 : 1
External pin STDAC trigger
#010 : 2
Timer 0 trigger
#011 : 3
Timer 1 trigger
#100 : 4
Timer 2 trigger
#101 : 5
Timer 3 trigger
#110 : 6
PWM0 trigger
#111 : 7
PWM1 trigger
End of enumeration elements list.
BYPASS : Bypass Buffer Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output voltage buffer Enabled
#1 : 1
Output voltage buffer Disabled
End of enumeration elements list.
LALIGN : DAC Data Left-aligned Enabled Control
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Right alignment
#1 : 1
Left alignment
End of enumeration elements list.
ETRGSEL : External Pin Trigger Selection
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Low level trigger
#01 : 1
High level trigger
#10 : 2
Falling edge trigger
#11 : 3
Rising edge trigger
End of enumeration elements list.
DAC Status Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FINISH : DAC Conversion Complete Finish Flag\nThis bit set to 1 when conversion time counter counts to SETTLET. It is cleared to 0 when DAC starts a new conversion. User writes 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC is in conversion state
#1 : 1
DAC conversion finish
End of enumeration elements list.
DMAUDR : DMA Under Run Interrupt Flag\nUser writes 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No DMA under-run error condition occurred
#1 : 1
DMA under-run error condition occurred
End of enumeration elements list.
BUSY : DAC Busy Flag (Read Only)\nThis is read only bit.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
DAC is ready for next conversion
#1 : 1
DAC is busy in conversion
End of enumeration elements list.
DAC Timing Control Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETTLET : DAC Output Settling Time\nUser software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.\nFor example, DAC controller clock speed is 72MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x48.
bits : 0 - 9 (10 bit)
access : read-write
DAC Software Trigger Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWTRG : Software Trigger
User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically Reading this bit will always get 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Software trigger Disabled
#1 : 1
Software trigger Enabled
End of enumeration elements list.
DAC Data Holding Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAC_DAT : DAC 12-bit Holding Data\nThese bits are written by user software which specifies 12-bit conversion data for DAC output. The unused bits (DAC_DAT[3:0] in left-alignment mode and DAC_DAT[15:12] in right alignment mode) are ignored by DAC controller hardware.\n12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.\n12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
bits : 0 - 15 (16 bit)
access : read-write
DAC Data Output Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATOUT : DAC 12-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC_DAT register and user cannot write it directly.
bits : 0 - 11 (12 bit)
access : read-only
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