\n
address_offset : 0x480 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x400 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x434 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
PDMA Channel Control Register
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHENn : PDMA Channel Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote1: If software stops the corresponding PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.\nNote2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.
bits : 0 - 11 (12 bit)
access : read-write
Enumeration:
0 : 0
PDMA channel [n] Disabled
1 : 1
PDMA channel [n] Enabled
End of enumeration elements list.
PDMA Transfer Stop Control Register
address_offset : 0x404 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
STOPn : PDMA Transfer Stop Control Register (Write Only)\nUser can stop the PDMA transfer by STOPn bit field or by software reset (writing '0xFFFF_FFFF' to PDMA_STOP register).\nBy bit field:\nBy write 0xFFFF_FFFF to PDMA_STOP:\nSetting all PDMA_STOP bit to '1' will generate software reset to reset internal state machine (the DSCT will not be reset). When software reset, the operation will be stopped imminently that include the on-going transfer and the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag will be cleared to '0'. \nNote1: User can read channel enable bit to know if the on-going transfer is finished.
bits : 0 - 11 (12 bit)
access : write-only
Enumeration:
0 : 0
No effect
1 : 1
Stop PDMA transfer[n]. When software set PDMA_STOP bit, the operation will finish the on-going transfer channel and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag
End of enumeration elements list.
PDMA Software Request Register
address_offset : 0x408 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWREQn : PDMA Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 0 - 11 (12 bit)
access : write-only
Enumeration:
0 : 0
No effect
1 : 1
Generate a software request
End of enumeration elements list.
PDMA Channel Request Status Register
address_offset : 0x40C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REQSTSn : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote1: If software stops corresponding PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.\nNote2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.
bits : 0 - 11 (12 bit)
access : read-only
Enumeration:
0 : 0
PDMA Channel n has no request
1 : 1
PDMA Channel n has a request
End of enumeration elements list.
PDMA Fixed Priority Setting Register
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPRISETn : PDMA Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote1: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 0 - 11 (12 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nCorresponding PDMA channel is round-robin priority
1 : 1
Set PDMA channel [n] to fixed priority channel.\nCorresponding PDMA channel is fixed priority
End of enumeration elements list.
PDMA Fixed Priority Clear Register
address_offset : 0x414 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FPRICLRn : PDMA Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote1: User can read PDMA_PRISET register to know the channel priority.
bits : 0 - 11 (12 bit)
access : write-only
Enumeration:
0 : 0
No effect
1 : 1
Clear PDMA channel [n] fixed priority setting
End of enumeration elements list.
PDMA Interrupt Enable Register
address_offset : 0x418 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTENn : PDMA Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.
bits : 0 - 11 (12 bit)
access : read-write
Enumeration:
0 : 0
PDMA channel n interrupt Disabled
1 : 1
PDMA channel n interrupt Enabled
End of enumeration elements list.
PDMA Interrupt Status Register
address_offset : 0x41C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABTIF : PDMA Read/Write Target Abort Interrupt Flag (Read-only)\nThis bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AHB bus ERROR response received
#1 : 1
AHB bus ERROR response received
End of enumeration elements list.
TDIF : Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not finished yet
#1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
TEIF : Table Empty Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished each table transmission and the operation is Stop mode. User can read TEIF register to indicate which channel finished transfer.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA channel transfer is not finished
#1 : 1
PDMA channel transfer is finished and the operation is in idle state
End of enumeration elements list.
REQTOFn : Request Time-out Flag for Each Channel [N]\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
0 : 0
No request time-out
1 : 1
Peripheral request time-out
End of enumeration elements list.
PDMA Channel Read/Write Target Abort Flag Register
address_offset : 0x420 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABTIFn : PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
bits : 0 - 11 (12 bit)
access : read-write
Enumeration:
0 : 0
No AHB bus ERROR response received when channel n transfer
1 : 1
AHB bus ERROR response received when channel n transfer
End of enumeration elements list.
PDMA Channel Transfer Done Flag Register
address_offset : 0x424 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDIFn : Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 0 - 11 (12 bit)
access : read-write
Enumeration:
0 : 0
PDMA channel transfer has not finished
1 : 1
PDMA channel has finished transmission
End of enumeration elements list.
PDMA Scatter-gather Table Empty Status Register
address_offset : 0x428 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEMPTYFn : Scatter-gather Table Empty Flag Register\nThis bit indicates which PDMA channel n Scatter Gather table is empty when SWREQn (PDMA_SWREQ[11:0]) set to high or channel has finished transmission and the operation mode is Stop mode. User can write 1 to clear these bits.
bits : 0 - 11 (12 bit)
access : read-write
Enumeration:
0 : 0
PDMA channel scatter-gather table is not empty
1 : 1
PDMA channel scatter-gather table is empty and PDMA SWREQ has be set
End of enumeration elements list.
PDMA Transfer Active Flag Register
address_offset : 0x42C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXACTFn : Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 0 - 11 (12 bit)
access : read-only
Enumeration:
0 : 0
PDMA channel is not finished
1 : 1
PDMA channel is active
End of enumeration elements list.
PDMA Time-out Enable Register
address_offset : 0x434 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUTENn : PDMA Time-out Enable Bits
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
PDMA Channel n time-out function Disable
1 : 1
PDMA Channel n time-out function Enable
End of enumeration elements list.
PDMA Time-out Interrupt Enable Register
address_offset : 0x438 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUTIENn : PDMA Time-out Interrupt Enable Bits
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
PDMA Channel n time-out interrupt Disable
1 : 1
PDMA Channel n time-out interrupt Enable
End of enumeration elements list.
PDMA Scatter-gather Descriptor Table Base Address Register
address_offset : 0x43C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCATBA : PDMA Scatter-gather Descriptor Table Address Register\nIn Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-Gather mode.
bits : 16 - 31 (16 bit)
access : read-write
PDMA Time-out Counter Ch1 and Ch0 Register
address_offset : 0x440 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOC0 : Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0. The calculation unit is based on 10 kHz clock.
bits : 0 - 15 (16 bit)
access : read-write
TOC1 : Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1. The calculation unit is based on 10 kHz clock.
bits : 16 - 31 (16 bit)
access : read-write
PDMA Time-out Counter Ch3 and Ch2 Register
address_offset : 0x444 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOC2 : Time-out Period Counter for Channel 2\nThis controls the period of time-out function for channel 2. The calculation unit is based on 10 kHz clock.
bits : 0 - 15 (16 bit)
access : read-write
TOC3 : Time-out Period Counter for Channel 3\nThis controls the period of time-out function for channel 3. The calculation unit is based on 10 kHz clock.
bits : 16 - 31 (16 bit)
access : read-write
PDMA Time-out Counter Ch5 and Ch4 Register
address_offset : 0x448 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOC4 : Time-out Period Counter for Channel 4\nThis controls the period of time-out function for channel 4. The calculation unit is based on 10 kHz clock.
bits : 0 - 15 (16 bit)
access : read-write
TOC5 : Time-out Period Counter for Channel 5\nThis controls the period of time-out function for channel 5. The calculation unit is based on 10 kHz clock.
bits : 16 - 31 (16 bit)
access : read-write
PDMA Time-out Counter Ch7 and Ch6 Register
address_offset : 0x44C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOC6 : Time-out Period Counter for Channel 6\nThis controls the period of time-out function for channel 6. The calculation unit is based on 10 kHz clock.
bits : 0 - 15 (16 bit)
access : read-write
TOC7 : Time-out Period Counter for Channel 7\nThis controls the period of time-out function for channel 7. The calculation unit is based on 10 kHz clock.
bits : 16 - 31 (16 bit)
access : read-write
PDMA Request Source Select Register 0
address_offset : 0x480 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQSRC0 : Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.\nNote 1: A peripheral can't assign to two channels at the same time.\nNote 2: This field is useless when transfer between memory and memory.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
1 : 1
Channel connects to SPI0_TX
2 : 2
Channel connects to SPI1_TX
3 : 3
Reserved.
4 : 4
Channel connects to UART0_TX
5 : 5
Channel connects to UART1_TX
6 : 6
Channel connects to UART2_TX
7 : 7
Channel connects to UART3_TX
8 : 8
Reserved.
9 : 9
Channel connects to ADC_RX
11 : 11
Channel connects to PWM0_P1_RX
12 : 12
Channel connects to PWM0_P2_RX
13 : 13
Channel connects to PWM0_P3_RX
14 : 14
Channel connects to PWM1_P1_RX
15 : 15
Channel connects to PWM1_P2_RX
16 : 16
Channel connects to PWM1_P3_RX
17 : 17
Channel connects to SPI0_RX
18 : 18
Channel connects to SPI1_RX
19 : 19
Reserved.
20 : 20
Channel connects to UART0_RX
21 : 21
Channel connects to UART1_RX
22 : 22
Channel connects to UART2_RX
23 : 23
Channel connects to UART3_RX
31 : 31
Disable PDMA
End of enumeration elements list.
REQSRC1 : Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 12 (5 bit)
access : read-write
REQSRC2 : Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 20 (5 bit)
access : read-write
REQSRC3 : Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 28 (5 bit)
access : read-write
PDMA Request Source Select Register 1
address_offset : 0x484 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REQSRC4 : Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 0 - 4 (5 bit)
access : read-write
REQSRC5 : Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 12 (5 bit)
access : read-write
REQSRC6 : Channel 6 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 20 (5 bit)
access : read-write
REQSRC7 : Channel 7 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 28 (5 bit)
access : read-write
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