Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1EC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x400 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1F4 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xE4 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
Part Device Identification Number Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDID : Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only
Peripheral Reset Control Register 2
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SC0RST : SC0 Controller Reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC0 controller normal operation
#1 : 1
SC0 controller reset
End of enumeration elements list.
SC1RST : SC1 Controller Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC1 controller normal operation
#1 : 1
SC1 controller reset
End of enumeration elements list.
SC2RST : SC2 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC2 controller normal operation
#1 : 1
SC2 controller reset
End of enumeration elements list.
QSPI1RST : QSPI1 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
QSPI1 controller normal operation
#1 : 1
QSPI1 controller reset
End of enumeration elements list.
SPI3RST : SPI3 Controller Reset
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI3 controller normal operation
#1 : 1
SPI3 controller reset
End of enumeration elements list.
USCI0RST : USCI0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI0 controller normal operation
#1 : 1
USCI0 controller reset
End of enumeration elements list.
USCI1RST : USCI1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI1 controller normal operation
#1 : 1
USCI1 controller reset
End of enumeration elements list.
DACRST : DAC Controller Reset
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
DAC controller normal operation
#1 : 1
DAC controller reset
End of enumeration elements list.
EPWM0RST : EPWM0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM0 controller normal operation
#1 : 1
EPWM0 controller reset
End of enumeration elements list.
EPWM1RST : EPWM1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM1 controller normal operation
#1 : 1
EPWM1 controller reset
End of enumeration elements list.
BPWM0RST : BPWM0 Controller Reset
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0 controller normal operation
#1 : 1
BPWM0 controller reset
End of enumeration elements list.
BPWM1RST : BPWM1 Controller Reset
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM1 controller normal operation
#1 : 1
BPWM1 controller reset
End of enumeration elements list.
QEI0RST : QEI0 Controller Reset
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEI0 controller normal operation
#1 : 1
QEI0 controller reset
End of enumeration elements list.
QEI1RST : QEI1 Controller Reset
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEI1 controller normal operation
#1 : 1
QEI1 controller reset
End of enumeration elements list.
ECAP0RST : ECAP0 Controller Reset
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECAP0 controller normal operation
#1 : 1
ECAP0 controller reset
End of enumeration elements list.
ECAP1RST : ECAP1 Controller Reset
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECAP1 controller normal operation
#1 : 1
ECAP1 controller reset
End of enumeration elements list.
CAN2RST : CAN2 Controller Reset
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
CAN2 controller normal operation
#1 : 1
CAN2 controller reset
End of enumeration elements list.
OPARST : OP Amplifier (OPA) Controller Reset
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
OPA controller normal operation
#1 : 1
OPA controller reset
End of enumeration elements list.
EADC1RST : EADC1 Controller Reset
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADC1 controller normal operation
#1 : 1
EADC1 controller reset
End of enumeration elements list.
Register Lock Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGLCTL : Register Lock Control Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h', '16h', '88h' to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.\n\nREGLCTL[0]\nRegister Lock Control Disable Index (Read Only)
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
1 : 1
Write-protection Disabled for writing protected registers
End of enumeration elements list.
Brown-out Detector Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODEN : Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector function Disabled
#1 : 1
Brown-out Detector function Enabled
End of enumeration elements list.
BODRSTEN : Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit.\nNote 1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).\nWhile the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out 'INTERRUPT' function Enabled
#1 : 1
Brown-out 'RESET' function Enabled
End of enumeration elements list.
BODIF : Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting
#1 : 1
When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled
End of enumeration elements list.
BODLPM : Brown-out Detector Low Power Mode (Write Protect)\nNote 1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
BOD operate in normal mode (default)
#1 : 1
BOD Low Power mode Enabled
End of enumeration elements list.
BODOUT : Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled, this bit always responds 0000.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector output status is 0
#1 : 1
Brown-out Detector output status is 1
End of enumeration elements list.
LVREN : Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote 1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default).\nNote 2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low Voltage Reset function Disabled
#1 : 1
Low Voltage Reset function Enabled
End of enumeration elements list.
BODDGSEL : Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
BOD output is sampled by RC10K clock
#001 : 1
4 system clock (HCLK)
#010 : 2
8 system clock (HCLK)
#011 : 3
16 system clock (HCLK)
#100 : 4
32 system clock (HCLK)
#101 : 5
64 system clock (HCLK)
#110 : 6
128 system clock (HCLK)
#111 : 7
256 system clock (HCLK)
End of enumeration elements list.
LVRDGSEL : LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Without de-glitch function
#001 : 1
4 system clock (HCLK)
#010 : 2
8 system clock (HCLK)
#011 : 3
16 system clock (HCLK)
#100 : 4
32 system clock (HCLK)
#101 : 5
64 system clock (HCLK)
#110 : 6
128 system clock (HCLK)
#111 : 7
256 system clock (HCLK)
End of enumeration elements list.
BODVL : Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by Flash controller user configuration register CBOV (CONFIG0 [23:21]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Brown-Out Detector threshold voltage is 1.6V
#001 : 1
Brown-Out Detector threshold voltage is 1.8V
#010 : 2
Brown-Out Detector threshold voltage is 2.0V
#011 : 3
Brown-Out Detector threshold voltage is 2.2V
#100 : 4
Brown-Out Detector threshold voltage is 2.4V
#101 : 5
Brown-Out Detector threshold voltage is 2.6V
#110 : 6
Brown-Out Detector threshold voltage is 2.8V
#111 : 7
Brown-Out Detector threshold voltage is 3.0V
End of enumeration elements list.
Internal Voltage Source Control Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTEMPEN : Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Temperature sensor function Disabled (default)
#1 : 1
Temperature sensor function Enabled
End of enumeration elements list.
VBATUGEN : VBAT Unity Gain Buffer Enable Bit\nThis bit is used to enable/disable VBAT unity gain buffer function.\nNote: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
VBAT unity gain buffer function Disabled (default)
#1 : 1
VBAT unity gain buffer function Enabled
End of enumeration elements list.
Analog POR Disable Control Register
address_offset : 0x1EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POROFFAN : Power-on Reset Enable Bit (Write Protect)
After powered on, User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field.
The analog POR circuit will be active again when this field is set to another value or chip is reset by other reset source, including:
nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
Note: M479 series will disable POR by hardware when system enter power-down mode.
bits : 0 - 15 (16 bit)
access : read-write
Chip Series Version Register
address_offset : 0x1F4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Chip Series Version\nThese bits indicate the series version of chip.
bits : 0 - 7 (8 bit)
access : read-only
Enumeration:
00 : 0
M479
01 : 1
M479
End of enumeration elements list.
Power Level Control Register
address_offset : 0x1F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLSEL : Power Level Select(Write Protect)\nThese bits indicate the status of power level.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Power level is PL0
#01 : 1
Power level is PL1
End of enumeration elements list.
LVSSTEP : LDO Voltage Scaling Step(Write Protect)\nThe LVSSTEP value is LDO voltage rising step.
bits : 16 - 21 (6 bit)
access : read-write
LVSPRD : LDO Voltage Scaling Period(Write Protect)\nThe LVSPRD value is the period of each LDO voltage rising step.
bits : 24 - 31 (8 bit)
access : read-write
Power Level Status Register
address_offset : 0x1FC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PLCBUSY : Power Level Change Busy Bit (Read Only)\nThis bit is set by hardware when power level is changing. After power level change is completed, this bit will be cleared automatically by hardware.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Core voltage change is completed
#1 : 1
Core voltage change is ongoing
End of enumeration elements list.
PLSTATUS : Power Level Status (Read Only)\nThis bit indicates the status of power level.
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
#00 : 0
Power level is PL0
#01 : 1
Power level is PL1
End of enumeration elements list.
VREF Control Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREFCTL : VREF Control Bits (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
#00000 : 0
VREF is from external pin
#00011 : 3
VREF is internal 1.6V
#00111 : 7
VREF is internal 2.0V
#01011 : 11
VREF is internal 2.5V
#01111 : 15
VREF is internal 3.0V
End of enumeration elements list.
PRELOAD_SEL : Pre-load Timing Selection (Write Protect)
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
pre-load time is 60us for 0.1uF Capacitor
#01 : 1
pre-load time is 310us for 1uF Capacitor
#10 : 2
pre-load time is 1270us for 4.7uF Capacitor
#11 : 3
pre-load time is 2650us for 10uF Capacitor
End of enumeration elements list.
VBGFEN : Chip Internal Voltage Bandgap Force Enable Bit(Write Only)
bits : 24 - 24 (1 bit)
access : write-only
Enumeration:
#0 : 0
Chip internal voltage bandgap controlled by ADC/ACMP if source selected
#1 : 1
Chip internal voltage bandgap force enable
End of enumeration elements list.
VBGISEL : Chip Internal Voltage Bandgap Current Selection Bits (Write Only)\nNote: When ADC conversion source select bandgap voltage, suggest set VBGISEL as 10.
bits : 25 - 26 (2 bit)
access : write-only
Enumeration:
#00 : 0
Bandgap voltage buffer current is 4.2uA
#01 : 1
Bandgap voltage buffer current is 7.3uA
#10 : 2
Bandgap voltage buffer current is 10.4uA
#11 : 3
Bandgap voltage buffer current is 13.5uA
End of enumeration elements list.
USB PHY Control Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBROLE : USB Role Option (Write Protect)\nThese two bits are used to select the role of USB.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Standard USB Device mode
#01 : 1
Standard USB Host mode
#10 : 2
ID dependent mode
#11 : 3
On-The-Go device mode
End of enumeration elements list.
SBO : Note: This bit must always be kept 1. If set to 0, the result is unpredictable
bits : 2 - 2 (1 bit)
access : read-write
USBEN : USB PHY Enable\nThis bit is used to enable/disable USB PHY.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB PHY Disabled
#1 : 1
USB PHY Enabled
End of enumeration elements list.
HSUSBROLE : HSUSB Role Option (Write Protect)\nThese two bits are used to select the role of HSUSB\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Standard HSUSB Device mode
#01 : 1
Standard HSUSB Host mode
#10 : 2
ID dependent mode
#11 : 3
On-The-Go device mode
End of enumeration elements list.
HSUSBEN : HSUSB PHY Enable\nThis bit is used to enable/disable HSUSB PHY.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
HSUSB PHY Disabled
#1 : 1
HSUSB PHY Enabled
End of enumeration elements list.
HSUSBACT : HSUSB PHY Active Control\nThis bit is used to control HSUSB PHY at reset state or active state\nNote: After set HSUSBEN (SYS_USBPHY[24]) to enable HSUSB PHY, user should keep HSUSB PHY at reset mode at lease 10uS before changing to active mode
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
HSUSB PHY at reset state
#1 : 1
HSUSB PHY at active state
End of enumeration elements list.
GPIOA Low Byte Multiple Function Control Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA0MFP : PA.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PA1MFP : PA.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PA2MFP : PA.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PA3MFP : PA.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PA4MFP : PA.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PA5MFP : PA.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PA6MFP : PA.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PA7MFP : PA.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOA High Byte Multiple Function Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA8MFP : PA.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PA9MFP : PA.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PA10MFP : PA.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PA11MFP : PA.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PA12MFP : PA.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PA13MFP : PA.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PA14MFP : PA.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PA15MFP : PA.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOB Low Byte Multiple Function Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PB1MFP : PB.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PB2MFP : PB.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PB3MFP : PB.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PB4MFP : PB.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PB5MFP : PB.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PB6MFP : PB.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PB7MFP : PB.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOB High Byte Multiple Function Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB8MFP : PB.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PB9MFP : PB.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PB10MFP : PB.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PB11MFP : PB.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PB12MFP : PB.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PB13MFP : PB.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PB14MFP : PB.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PB15MFP : PB.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
System Reset Status Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORF : POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from POR or CHIPRST
#1 : 1
Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system
End of enumeration elements list.
PINRF : NRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from nRESET pin
#1 : 1
Pin nRESET had issued the reset signal to reset the system
End of enumeration elements list.
WDTRF : WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\nNote 1: Write 1 to clear this bit to 0.\nNote 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from watchdog timer or window watchdog timer
#1 : 1
The watchdog timer or window watchdog timer had issued the reset signal to reset the system
End of enumeration elements list.
LVRF : LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from LVR
#1 : 1
LVR controller had issued the reset signal to reset the system
End of enumeration elements list.
BODRF : BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from BOD
#1 : 1
The BOD had issued the reset signal to reset the system
End of enumeration elements list.
SYSRF : System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the Cortex-M4 Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from Cortex-M4
#1 : 1
The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core
End of enumeration elements list.
HRESETRF : HRESET Reset Flag\nThe HRESET reset flag is set by the 'Reset Signal' from the HRESET.\nNote: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from HRESET
#1 : 1
Reset from HRESET
End of enumeration elements list.
CPURF : CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from CPU
#1 : 1
The Cortex-M4 Core and FMC are reset by software setting CPURST to 1
End of enumeration elements list.
CPULKRF : CPU Lockup Reset Flag\nNote 1: Write 1 to clear this bit to 0.\nNote 2: When CPU lockup happened under ICE is connected, this flag will set to 1 but chip will not reset.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from CPU lockup happened
#1 : 1
The Cortex-M4 lockup happened and chip is reset
End of enumeration elements list.
GPIOC Low Byte Multiple Function Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC0MFP : PC.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PC1MFP : PC.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PC2MFP : PC.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PC3MFP : PC.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PC4MFP : PC.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PC5MFP : PC.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PC6MFP : PC.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PC7MFP : PC.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
AHB Bus Matrix Priority Control Register
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTACTEN : Highest AHB Bus Priority of Cortex-M4 Core Enable Bit (Write Protect)\nEnable Cortex-M4 Core With Highest AHB Bus Priority In AHB Bus Matrix\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Round-robin mode
#1 : 1
Cortex-M4 CPU with highest bus priority when interrupt occurred
End of enumeration elements list.
GPIOC High Byte Multiple Function Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC8MFP : PC.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PC9MFP : PC.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PC10MFP : PC.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PC11MFP : PC.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PC12MFP : PC.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PC13MFP : PC.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PC14MFP : PC.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PC15MFP : PC.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOD Low Byte Multiple Function Control Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0MFP : PD.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PD1MFP : PD.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PD2MFP : PD.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PD3MFP : PD.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PD4MFP : PD.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PD5MFP : PD.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PD6MFP : PD.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PD7MFP : PD.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOD High Byte Multiple Function Control Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD8MFP : PD.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PD9MFP : PD.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PD10MFP : PD.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PD11MFP : PD.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PD12MFP : PD.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PD13MFP : PD.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PD14MFP : PD.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PD15MFP : PD.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOE Low Byte Multiple Function Control Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE0MFP : PE.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PE1MFP : PE.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PE2MFP : PE.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PE3MFP : PE.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PE4MFP : PE.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PE5MFP : PE.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PE6MFP : PE.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PE7MFP : PE.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOE High Byte Multiple Function Control Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE8MFP : PE.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PE9MFP : PE.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PE10MFP : PE.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PE11MFP : PE.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PE12MFP : PE.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PE13MFP : PE.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PE14MFP : PE.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PE15MFP : PE.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOF Low Byte Multiple Function Control Register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF0MFP : PF.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PF1MFP : PF.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PF2MFP : PF.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PF3MFP : PF.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PF4MFP : PF.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PF5MFP : PF.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PF6MFP : PF.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PF7MFP : PF.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOF High Byte Multiple Function Control Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF8MFP : PF.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PF9MFP : PF.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PF10MFP : PF.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PF11MFP : PF.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PF12MFP : PF.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PF13MFP : PF.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PF14MFP : PF.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PF15MFP : PF.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOG Low Byte Multiple Function Control Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG0MFP : PG.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PG1MFP : PG.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PG2MFP : PG.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PG3MFP : PG.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PG4MFP : PG.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PG5MFP : PG.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PG6MFP : PG.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PG7MFP : PG.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOG High Byte Multiple Function Control Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG8MFP : PG.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PG9MFP : PG.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PG10MFP : PG.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PG11MFP : PG.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PG12MFP : PG.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PG13MFP : PG.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PG14MFP : PG.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PG15MFP : PG.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOH Low Byte Multiple Function Control Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH0MFP : PH.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PH1MFP : PH.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PH2MFP : PH.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PH3MFP : PH.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PH4MFP : PH.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PH5MFP : PH.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PH6MFP : PH.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PH7MFP : PH.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOH High Byte Multiple Function Control Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH8MFP : PH.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PH9MFP : PH.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PH10MFP : PH.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PH11MFP : PH.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PH12MFP : PH.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PH13MFP : PH.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PH14MFP : PH.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PH15MFP : PH.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Peripheral Reset Control Register 0
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIPRST : Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from Flash are also reload.\nAbout the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 7.2.2\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip normal operation
#1 : 1
Chip one-shot reset
End of enumeration elements list.
CPURST : Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Processor core normal operation
#1 : 1
Processor core one-shot reset
End of enumeration elements list.
PDMARST : PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA controller normal operation
#1 : 1
PDMA controller reset
End of enumeration elements list.
EBIRST : EBI Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI controller normal operation
#1 : 1
EBI controller reset
End of enumeration elements list.
EMACRST : EMAC Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the EMAC controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
EMAC controller normal operation
#1 : 1
EMAC controller reset
End of enumeration elements list.
SDH0RST : SDHOST0 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the SDHOST0 controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SDHOST0 controller normal operation
#1 : 1
SDHOST0 controller reset
End of enumeration elements list.
CRCRST : CRC Calculation Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRC calculation controller normal operation
#1 : 1
CRC calculation controller reset
End of enumeration elements list.
CCAPRST : CCAP Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CCAP controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
CCAP controller normal operation
#1 : 1
CCAP controller reset
End of enumeration elements list.
HSUSBDRST : HSUSBD Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the HSUSBD controller. User needs to set this bit to 0 to release from the reset state.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
HSUSBD controller normal operation
#1 : 1
HSUSBD controller reset
End of enumeration elements list.
CRPTRST : CRYPTO Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the CRYPTO controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRYPTO controller normal operation
#1 : 1
CRYPTO controller reset
End of enumeration elements list.
SPIMRST : SPIM Controller Reset\nSetting this bit to 1 will generate a reset signal to the SPIM controller. User needs to set this bit to 0 to release from the reset state.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPIM controller normal operation
#1 : 1
SPIM controller reset
End of enumeration elements list.
HSUSBHRST : HSUSBH Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the HSUSBH controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
HSUSBH controller normal operation
#1 : 1
HSUSBH controller reset
End of enumeration elements list.
SDH1RST : SDHOST1 Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the SDHOST1 controller. User needs to set this bit to 0 to release from the reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
SDHOST1 controller normal operation
#1 : 1
SDHOST1 controller reset
End of enumeration elements list.
GPIOA Multiple Function Output Select Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MFOS0 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple function pin output mode type is Push-pull mode
#1 : 1
Multiple function pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS1 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple function pin output mode type is Push-pull mode
#1 : 1
Multiple function pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS2 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple function pin output mode type is Push-pull mode
#1 : 1
Multiple function pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS3 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple function pin output mode type is Push-pull mode
#1 : 1
Multiple function pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS4 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple function pin output mode type is Push-pull mode
#1 : 1
Multiple function pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS5 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple function pin output mode type is Push-pull mode
#1 : 1
Multiple function pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS6 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple function pin output mode type is Push-pull mode
#1 : 1
Multiple function pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS7 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple function pin output mode type is Push-pull mode
#1 : 1
Multiple function pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS8 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple function pin output mode type is Push-pull mode
#1 : 1
Multiple function pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS9 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple function pin output mode type is Push-pull mode
#1 : 1
Multiple function pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS10 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple function pin output mode type is Push-pull mode
#1 : 1
Multiple function pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS11 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple function pin output mode type is Push-pull mode
#1 : 1
Multiple function pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS12 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple function pin output mode type is Push-pull mode
#1 : 1
Multiple function pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS13 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple function pin output mode type is Push-pull mode
#1 : 1
Multiple function pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS14 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple function pin output mode type is Push-pull mode
#1 : 1
Multiple function pin output mode type is Open-drain mode
End of enumeration elements list.
MFOS15 : GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Multiple function pin output mode type is Push-pull mode
#1 : 1
Multiple function pin output mode type is Open-drain mode
End of enumeration elements list.
GPIOB Multiple Function Output Select Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOC Multiple Function Output Select Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOD Multiple Function Output Select Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOE Multiple Function Output Select Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOF Multiple Function Output Select Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOG Multiple Function Output Select Register
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIOH Multiple Function Output Select Register
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Peripheral Reset Control Register 1
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIORST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO controller normal operation
#1 : 1
GPIO controller reset
End of enumeration elements list.
TMR0RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 controller normal operation
#1 : 1
Timer0 controller reset
End of enumeration elements list.
TMR1RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 controller normal operation
#1 : 1
Timer1 controller reset
End of enumeration elements list.
TMR2RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 controller normal operation
#1 : 1
Timer2 controller reset
End of enumeration elements list.
TMR3RST : Timer3 Controller Reset
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 controller normal operation
#1 : 1
Timer3 controller reset
End of enumeration elements list.
ACMP01RST : Analog Comparator 0/1 Controller Reset
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator 0/1 controller normal operation
#1 : 1
Analog Comparator 0/1 controller reset
End of enumeration elements list.
I2C0RST : I2C0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0 controller normal operation
#1 : 1
I2C0 controller reset
End of enumeration elements list.
I2C1RST : I2C1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C1 controller normal operation
#1 : 1
I2C1 controller reset
End of enumeration elements list.
I2C2RST : I2C2 Controller Reset
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C2 controller normal operation
#1 : 1
I2C2 controller reset
End of enumeration elements list.
QSPI0RST : Qual SPI0 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Qual SPI0 controller normal operation
#1 : 1
Qual SPI0 controller reset
End of enumeration elements list.
SPI0RST : SPI0 Controller Reset
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 controller normal operation
#1 : 1
SPI0 controller reset
End of enumeration elements list.
SPI1RST : SPI1 Controller Reset
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI1 controller normal operation
#1 : 1
SPI1 controller reset
End of enumeration elements list.
SPI2RST : SPI2 Controller Reset
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI2 controller normal operation
#1 : 1
SPI2 controller reset
End of enumeration elements list.
UART0RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 controller normal operation
#1 : 1
UART0 controller reset
End of enumeration elements list.
UART1RST : UART1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 controller normal operation
#1 : 1
UART1 controller reset
End of enumeration elements list.
UART2RST : UART2 Controller Reset
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART2 controller normal operation
#1 : 1
UART2 controller reset
End of enumeration elements list.
UART3RST : UART3 Controller Reset
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART3 controller normal operation
#1 : 1
UART3 controller reset
End of enumeration elements list.
UART4RST : UART4 Controller Reset
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART4 controller normal operation
#1 : 1
UART4 controller reset
End of enumeration elements list.
UART5RST : UART5 Controller Reset
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART5 controller normal operation
#1 : 1
UART5 controller reset
End of enumeration elements list.
UART6RST : UART6 Controller Reset
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART6 controller normal operation
#1 : 1
UART6 controller reset
End of enumeration elements list.
UART7RST : UART7 Controller Reset
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART7 controller normal operation
#1 : 1
UART7 controller reset
End of enumeration elements list.
CAN0RST : CAN0 Controller Reset
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
CAN0 controller normal operation
#1 : 1
CAN0 controller reset
End of enumeration elements list.
CAN1RST : CAN1 Controller Reset
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
CAN1 controller normal operation
#1 : 1
CAN1 controller reset
End of enumeration elements list.
OTGRST : OTG Controller Reset
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
OTG controller normal operation
#1 : 1
OTG controller reset
End of enumeration elements list.
USBDRST : USBD Controller Reset
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
USBD controller normal operation
#1 : 1
USBD controller reset
End of enumeration elements list.
EADCRST : EADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADC controller normal operation
#1 : 1
EADC controller reset
End of enumeration elements list.
I2S0RST : I2S0 Controller Reset
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2S0 controller normal operation
#1 : 1
I2S0 controller reset
End of enumeration elements list.
HSOTGRST : HSOTG Controller Reset
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
HSOTG controller normal operation
#1 : 1
HSOTG controller reset
End of enumeration elements list.
TRNGRST : TRNG Controller Reset
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
TRNG controller normal operation
#1 : 1
TRNG controller reset
End of enumeration elements list.
System SRAM Interrupt Enable Control Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERRIEN : SRAM Parity Check Error Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SRAM parity check error interrupt Disabled
#1 : 1
SRAM parity check error interrupt Enabled
End of enumeration elements list.
System SRAM Parity Error Status Register
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERRIF : SRAM Parity Check Error Flag\nThis bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No System SRAM parity error
#1 : 1
System SRAM parity error occur
End of enumeration elements list.
System SRAM Parity Check Error Address Register
address_offset : 0xC8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ERRADDR : System SRAM Parity Error Address\nThis register shows system SRAM parity error byte address.
bits : 0 - 31 (32 bit)
access : read-only
System SRAM BIST Test Control Register
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRBIST0 : SRAM Bank0 BIST Enable Bit (Write Protect)\nThis bit enables BIST test for SRAM bank0.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
system SRAM bank0 BIST Disabled
#1 : 1
system SRAM bank0 BIST Enabled
End of enumeration elements list.
SRBIST1 : SRAM Bank1 BIST Enable Bit (Write Protect)\nThis bit enables BIST test for SRAM bank1.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
system SRAM bank1 BIST Disabled
#1 : 1
system SRAM bank1 BIST Enabled
End of enumeration elements list.
CRBIST : CACHE BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CACHE RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
system CACHE BIST Disabled
#1 : 1
system CACHE BIST Enabled
End of enumeration elements list.
CANBIST : CAN BIST Enable Bit (Write Protect)\nThis bit enables BIST test for CAN RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
system CAN BIST Disabled
#1 : 1
system CAN BIST Enabled
End of enumeration elements list.
USBBIST : USB BIST Enable Bit (Write Protect)\nThis bit enables BIST test for USB RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
system USB BIST Disabled
#1 : 1
system USB BIST Enabled
End of enumeration elements list.
SPIMBIST : SPIM BIST Enable Bit (Write Protect)\nThis bit enables BIST test for SPIM RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
system SPIM BIST Disabled
#1 : 1
system SPIM BIST Enabled
End of enumeration elements list.
EMCBIST : EMC BIST Enable Bit (Write Protect)\nThis bit enables BIST test for EMC RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
system EMC BIST Disabled
#1 : 1
system EMC BIST Enabled
End of enumeration elements list.
PDMABIST : PDMA BIST Enable Bit (Write Protect)\nThis bit enables BIST test for PDMA RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
system PDMA BIST Disabled
#1 : 1
system PDMA BIST Enabled
End of enumeration elements list.
HSUSBDBIST : HSUSBD BIST Enable Bit (Write Protect)\nThis bit enables BIST test for HSUSBD RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
system HSUSBD BIST Disabled
#1 : 1
system HSUSBD BIST Enabled
End of enumeration elements list.
HSUSBHBIST : HSUSBH BIST Enable Bit (Write Protect)\nThis bit enables BIST test for HSUSBH RAM\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
system HSUSBH BIST Disabled
#1 : 1
system HSUSBH BIST Enabled
End of enumeration elements list.
System SRAM BIST Test Status Register
address_offset : 0xD4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SRBISTEF0 : 1st System SRAM BIST Fail Flag
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
1st system SRAM BIST test pass
#1 : 1
1st system SRAM BIST test fail
End of enumeration elements list.
SRBISTEF1 : 2nd System SRAM BIST Fail Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
2nd system SRAM BIST test pass
#1 : 1
2nd system SRAM BIST test fail
End of enumeration elements list.
CRBISTEF : CACHE SRAM BIST Fail Flag
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
System CACHE RAM BIST test pass
#1 : 1
System CACHE RAM BIST test fail
End of enumeration elements list.
CANBEF : CAN SRAM BIST Fail Flag
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
CAN SRAM BIST test pass
#1 : 1
CAN SRAM BIST test fail
End of enumeration elements list.
USBBEF : USB SRAM BIST Fail Flag
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
USB SRAM BIST test pass
#1 : 1
USB SRAM BIST test fail
End of enumeration elements list.
PDMABEF : PDMA SRAM BIST Fail Flag
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA SRAM BIST test pass
#1 : 1
PDMA SRAM BIST test fail
End of enumeration elements list.
SRBEND0 : 1st SRAM BIST Test Finish
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
1st system SRAM BIST active
#1 : 1
1st system SRAM BIST finish
End of enumeration elements list.
SRBEND1 : 2nd SRAM BIST Test Finish
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
2nd system SRAM BIST is active
#1 : 1
2nd system SRAM BIST finish
End of enumeration elements list.
CRBEND : CACHE SRAM BIST Test Finish
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
System CACHE RAM BIST is active
#1 : 1
System CACHE RAM BIST test finish
End of enumeration elements list.
CANBEND : CAN SRAM BIST Test Finish
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
#0 : 0
CAN SRAM BIST is active
#1 : 1
CAN SRAM BIST test finish
End of enumeration elements list.
USBBEND : USB SRAM BIST Test Finish
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
USB SRAM BIST is active
#1 : 1
USB SRAM BIST test finish
End of enumeration elements list.
PDMABEND : PDMA SRAM BIST Test Finish
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
PDMA SRAM BIST is active
#1 : 1
PDMA SRAM BIST test finish
End of enumeration elements list.
HIRC48M Trim Control Register
address_offset : 0xE4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Disable HIRC auto trim function
#01 : 1
Enable HIRC auto trim function and trim HIRC to 48 MHz
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
LOOPSEL : Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim value calculation is based on average difference in 4 clocks of reference clock
#01 : 1
Trim value calculation is based on average difference in 8 clocks of reference clock
#10 : 2
Trim value calculation is based on average difference in 16 clocks of reference clock
#11 : 3
Trim value calculation is based on average difference in 32 clocks of reference clock
End of enumeration elements list.
RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim retry count limitation is 64 loops
#01 : 1
Trim retry count limitation is 128 loops
#10 : 2
Trim retry count limitation is 256 loops
#11 : 3
Trim retry count limitation is 512 loops
End of enumeration elements list.
CESTOPEN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The trim operation is keep going if clock is inaccuracy
#1 : 1
The trim operation is stopped if clock is inaccuracy
End of enumeration elements list.
BOUNDEN : Boundary Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Boundary function Disabled
#1 : 1
Boundary function Enabled
End of enumeration elements list.
REFCKSEL : Reference Clock Selection\nNote: HIRC trim reference clock is 20 kHz in test mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
HIRC trim reference clock is from LXT (32.768 kHz)
#1 : 1
HIRC trim reference clock is from internal USB synchronous mode
End of enumeration elements list.
BOUNDARY : Boundary Selection\nFill the boundary range from 0x1 to 0x31, 0x0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enabled.
bits : 16 - 20 (5 bit)
access : read-write
HIRC48M Trim Interrupt Enable Register
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFAILIEN : Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU
#1 : 1
Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU
End of enumeration elements list.
CLKEIEN : Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU
#1 : 1
Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU
End of enumeration elements list.
HIRC48M Trim Interrupt Status Register
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQLOCK : HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt\nWrite 1 to clear this to 0. This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The internal high-speed oscillator frequency doesn't lock at 48 MHz yet
#1 : 1
The internal high-speed oscillator frequency locked at 48 MHz
End of enumeration elements list.
TFAILIF : Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trim value update limitation count does not reach
#1 : 1
Trim value update limitation count reached and HIRC frequency still not locked
End of enumeration elements list.
CLKERRIF : Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock frequency is accuracy
#1 : 1
Clock frequency is inaccuracy
End of enumeration elements list.
OVBDIF : Over Boundary Status\nWhen the over boundary function is set, if there occurs the over boundary condition, this flag will be set.\nNote 1: Write 1 to clear this flag.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Over boundary coundition did not occur
#1 : 1
Over boundary coundition occurred
End of enumeration elements list.
HIRC Trim Control Register
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Disable HIRC auto trim function
#01 : 1
Enable HIRC auto trim function and trim HIRC to 12 MHz
#10 : 2
Reserved.
#11 : 3
Reserved.
End of enumeration elements list.
LOOPSEL : Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim value calculation is based on average difference in 4 clocks of reference clock
#01 : 1
Trim value calculation is based on average difference in 8 clocks of reference clock
#10 : 2
Trim value calculation is based on average difference in 16 clocks of reference clock
#11 : 3
Trim value calculation is based on average difference in 32 clocks of reference clock
End of enumeration elements list.
RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim retry count limitation is 64 loops
#01 : 1
Trim retry count limitation is 128 loops
#10 : 2
Trim retry count limitation is 256 loops
#11 : 3
Trim retry count limitation is 512 loops
End of enumeration elements list.
CESTOPEN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The trim operation is keep going if clock is inaccuracy
#1 : 1
The trim operation is stopped if clock is inaccuracy
End of enumeration elements list.
BOUNDEN : Boundary Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Boundary function Disabled
#1 : 1
Boundary function Enabled
End of enumeration elements list.
REFCKSEL : Reference Clock Selection\nNote: HIRC trim reference clock is 20 kHz in test mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
HIRC trim reference clock is from LXT (32.768 kHz)
#1 : 1
HIRC trim reference clock is from internal USB synchronous mode
End of enumeration elements list.
BOUNDARY : Boundary Selection\nFill the boundary range from 0x1 to 0x31, 0x0 is reserved.\nNote 1: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enabled.
bits : 16 - 20 (5 bit)
access : read-write
HIRC Trim Interrupt Enable Register
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFAILIEN : Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU
#1 : 1
Enable TFAILIF(SYS_IRCTISTS[1]) status to trigger an interrupt to CPU
End of enumeration elements list.
CLKEIEN : Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU
#1 : 1
Enable CLKERRIF(SYS_IRCTISTS[2]) status to trigger an interrupt to CPU
End of enumeration elements list.
HIRC Trim Interrupt Status Register
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQLOCK : HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt\nWrite 1 to clear this to 0. This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The internal high-speed oscillator frequency doesn't lock at 12 MHz yet
#1 : 1
The internal high-speed oscillator frequency locked at 12 MHz
End of enumeration elements list.
TFAILIF : Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trim value update limitation count does not reach
#1 : 1
Trim value update limitation count reached and HIRC frequency still not locked
End of enumeration elements list.
CLKERRIF : Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock frequency is accuracy
#1 : 1
Clock frequency is inaccuracy
End of enumeration elements list.
OVBDIF : Over Boundary Status\nWhen the over boundary function is set, if there occurs the over boundary condition, this flag will be set.\nNote 1: Write 1 to clear this flag.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Over boundary coundition did not occur
#1 : 1
Over boundary coundition occurred
End of enumeration elements list.
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