\n
address_offset : 0x10 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD0C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD18 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD04 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
SysTick Control and Status Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : System Tick Counter Enabled
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Counter Disabled
#1 : 1
Counter will operate in a multi-shot manner
End of enumeration elements list.
TICKINT : System Tick Interrupt Enabled
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Counting down to 0 does not cause the SysTick exception to be pended. Software can use COUNTFLAG to determine if a count to zero has occurred
#1 : 1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick current value register by a register write in software will not cause SysTick to be pended
End of enumeration elements list.
CLKSRC : System Tick Clock Source Selection
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source is the (optional) external reference clock
#1 : 1
Core clock used for SysTick
End of enumeration elements list.
COUNTFLAG : System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
bits : 16 - 16 (1 bit)
access : read-write
SysTick Reload Value Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD : System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0.
bits : 0 - 23 (24 bit)
access : read-write
SysTick Current Value Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURRENT : System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0.
bits : 0 - 23 (24 bit)
access : read-write
Interrupt Control and State Register
address_offset : 0xD04 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTACTIVE : Number of the Current Active Exception
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0 : 0
Thread mode
End of enumeration elements list.
RETTOBASE : Preempted Active Exceptions Indicator\nIndicate whether There are Preempted Active Exceptions
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
there are preempted active exceptions to execute
#1 : 1
there are no active exceptions, or the currently-executing exception is the only active exception
End of enumeration elements list.
VECTPENDING : Number of the Highest Pended Exception\nIndicate the Exception Number of the Highest Priority Pending Enabled Exception\nThe value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register.
bits : 12 - 17 (6 bit)
access : read-write
Enumeration:
0 : 0
No pending exceptions
End of enumeration elements list.
ISRPENDING : Interrupt Pending Flag, Excluding NMI and Faults (Read Only)
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not pending
#1 : 1
Interrupt pending
End of enumeration elements list.
ISRPREEMPT : Interrupt Preempt Bit (Read Only)\nIf set, a pending exception will be serviced on exit from the debug halt state.
bits : 23 - 23 (1 bit)
access : read-only
PENDSTRTC_CAL : SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDST bit, you must 'write 0 to PENDSTSET and write 1 to PENDSTRTC_CAL' at the same time.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Remove the pending state from the SysTick exception
End of enumeration elements list.
PENDSTSET : SysTick Exception Set-pending Bit\nWrite Operation:
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nSysTick exception is not pending
#1 : 1
Change SysTick exception state to pending.\nSysTick exception is pending
End of enumeration elements list.
PENDSVRTC_CAL : PendSV Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit. To clear the PENDSV bit, you must 'write 0 to PENDSVSET and write 1 to PENDSVRTC_CAL' at the same time.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Remove the pending state from the PendSV exception
End of enumeration elements list.
PENDSVSET : PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nPendSV exception is not pending
#1 : 1
Change PendSV exception state to pending.\nPendSV exception is pending
End of enumeration elements list.
NMIPENDSET : NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNMI exception is not pending
#1 : 1
Change NMI exception state to pending.\nNMI exception is pending
End of enumeration elements list.
Application Interrupt and Reset Control Register
address_offset : 0xD0C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTRESET : Reserved.
bits : 0 - 0 (1 bit)
access : read-write
VECTCLRACTIVE : Exception Active Status Clear Bit\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack.
bits : 1 - 1 (1 bit)
access : read-write
SYSRESETREQ : System Reset Request\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence.
bits : 2 - 2 (1 bit)
access : read-write
PRIGROUP : Interrupt Priority Grouping\nThis field determines the Split Of Group priority from subpriority,
bits : 8 - 10 (3 bit)
access : read-write
ENDIANNESS : Data Endianness
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Little-endian
#1 : 1
Big-endian
End of enumeration elements list.
VECTORKEY : Register Access Key\nWhen writing this register, this field should be 0x05FA, otherwise the write action will be unpredictable.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.
bits : 16 - 31 (16 bit)
access : read-write
System Control Register
address_offset : 0xD10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : Sleep-on-exit Enable Control\nThis bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not sleep when returning to Thread mode
#1 : 1
Enter sleep, or deep sleep, on return from an ISR to Thread mode
End of enumeration elements list.
SLEEPDEEP : Processor Deep Sleep and Sleep Mode Selection\nControl whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sleep
#1 : 1
Deep sleep
End of enumeration elements list.
SEVONPEND : Send Event on Pending\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Only enabled interrupts or events can wake up the processor, while disabled interrupts are excluded
#1 : 1
Enabled events and all interrupts, including disabled interrupts, can wake up the processor
End of enumeration elements list.
System Handler Priority Register 1
address_offset : 0xD18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4 : Priority of system handler 4, MemManage
bits : 4 - 7 (4 bit)
access : read-write
PRI_5 : Priority of system handler 5, BusFault
bits : 12 - 15 (4 bit)
access : read-write
PRI_6 : Priority of system handler 6, UsageFault
bits : 20 - 23 (4 bit)
access : read-write
System Handler Priority Register 2
address_offset : 0xD1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_11 : Priority of System Handler 11 - SVCall\n'0' denotes the highest priority and '3' denotes the lowest priority.
bits : 28 - 31 (4 bit)
access : read-write
System Handler Priority Register 3
address_offset : 0xD20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_14 : Priority of System Handler 14 - PendSV\n'0' denotes the highest priority and '3' denotes the lowest priority.
bits : 20 - 23 (4 bit)
access : read-write
PRI_15 : Priority of System Handler 15 - SysTick\n'0' denotes the highest priority and '3' denotes the lowest priority.
bits : 28 - 31 (4 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.