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PDMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x80 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x90 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xA0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xB0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x60 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x70 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xD0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xE0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xF0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PDMA_DSCT0_CTL

PDMA_DSCT1_CTL

PDMA_DSCT2_CTL

PDMA_DSCT3_CTL

PDMA_DSCT4_CTL

PDMA_DSCT5_CTL

PDMA_DSCT6_CTL

PDMA_DSCT7_CTL

PDMA_DSCT8_CTL

PDMA_DSCT9_CTL

PDMA_DSCT10_CTL

PDMA_DSCT11_CTL

PDMA_DSCT12_CTL

PDMA_DSCT13_CTL

PDMA_DSCT14_CTL

PDMA_DSCT15_CTL


PDMA_DSCT0_CTL

Descriptor Table Control Register of PDMA Channel n
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT0_CTL PDMA_DSCT0_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPMODE TXTYPE BURSIZE TBINTDIS SAINC DAINC TXWIDTH STRIDEEN TXCNT

OPMODE : PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table, user must check the PDMA_INTSTS[1] to make sure the curren task is complete.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically

#01 : 1

Basic mode: The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[1] will be asserted

#10 : 2

Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register PDMA controller will ignore this task, then load the next task to execute

#11 : 3

Reserved.

End of enumeration elements list.

TXTYPE : Transfer Type
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Burst transfer type

#1 : 1

Single transfer type

End of enumeration elements list.

BURSIZE : Burst Size\nNote: This field is only useful in burst transfer type.
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#000 : 0

128 Transfers

#001 : 1

64 Transfers

#010 : 2

32 Transfers

#011 : 3

16 Transfers

#100 : 4

8 Transfers

#101 : 5

4 Transfers

#110 : 6

2 Transfers

#111 : 7

1 Transfers

End of enumeration elements list.

TBINTDIS : Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled it will not generates TDIFn(PDMA_TDSTS[15:0]) when PDMA controller finishes transfer task.\nNote: This function only for scatter-gather mode.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Table interrupt Enabled

#1 : 1

Table interrupt Disabled

End of enumeration elements list.

SAINC : Source Address Increment\nThis field is used to set the source address increment size.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#11 : 3

No increment (fixed address)

End of enumeration elements list.

DAINC : Destination Address Increment\nThis field is used to set the destination address increment size.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#11 : 3

No increment (fixed address)

End of enumeration elements list.

TXWIDTH : Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

One byte (8 bit) is transferred for every operation

#01 : 1

One half-word (16 bit) is transferred for every operation

#10 : 2

One word (32-bit) is transferred for every operation

#11 : 3

Reserved.

End of enumeration elements list.

STRIDEEN : Stride Mode Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Stride transfer mode Disabled

#1 : 1

Stride transfer mode Enabled

End of enumeration elements list.

TXCNT : Transfer Count The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1) The maximum transfer count is 65536, every transfer may be byte, half-word or word that is dependent on TXWIDTH field. Note: When PDMA finish each transfer data, this field will be decrease immediately.
bits : 16 - 31 (16 bit)
access : read-write


PDMA_DSCT1_CTL

Descriptor Table Control Register of PDMA Channel n
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT1_CTL PDMA_DSCT1_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT2_CTL

Descriptor Table Control Register of PDMA Channel n
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT2_CTL PDMA_DSCT2_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT3_CTL

Descriptor Table Control Register of PDMA Channel n
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT3_CTL PDMA_DSCT3_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT4_CTL

Descriptor Table Control Register of PDMA Channel n
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT4_CTL PDMA_DSCT4_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT5_CTL

Descriptor Table Control Register of PDMA Channel n
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT5_CTL PDMA_DSCT5_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT6_CTL

Descriptor Table Control Register of PDMA Channel n
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT6_CTL PDMA_DSCT6_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT7_CTL

Descriptor Table Control Register of PDMA Channel n
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT7_CTL PDMA_DSCT7_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT8_CTL

Descriptor Table Control Register of PDMA Channel n
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT8_CTL PDMA_DSCT8_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT9_CTL

Descriptor Table Control Register of PDMA Channel n
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT9_CTL PDMA_DSCT9_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT10_CTL

Descriptor Table Control Register of PDMA Channel n
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT10_CTL PDMA_DSCT10_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT11_CTL

Descriptor Table Control Register of PDMA Channel n
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT11_CTL PDMA_DSCT11_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT12_CTL

Descriptor Table Control Register of PDMA Channel n
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT12_CTL PDMA_DSCT12_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT13_CTL

Descriptor Table Control Register of PDMA Channel n
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT13_CTL PDMA_DSCT13_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT14_CTL

Descriptor Table Control Register of PDMA Channel n
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT14_CTL PDMA_DSCT14_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT15_CTL

Descriptor Table Control Register of PDMA Channel n
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT15_CTL PDMA_DSCT15_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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