RTC_INIT (INIT)

RTC_CAL (CAL)

RTC_LXTCTL (LXTCTL)

RTC_GPIOCTL0 (GPIOCTL0)

RTC_GPIOCTL1 (GPIOCTL1)

RTC_DSTCTL (DSTCTL)

RTC_TAMPCTL (TAMPCTL)

RTC_TAMPSEED (TAMPSEED)

RTC_TAMPTIME (TAMPTIME)

RTC_TAMPCAL (TAMPCAL)

RTC_CLKFMT (CLKFMT)

RTC_WEEKDAY (WEEKDAY)

RTC_TALM (TALM)

RTC_CALM (CALM)

RTC_LEAPYEAR (LEAPYEAR)

RTC_INTEN (INTEN)

RTC_INTSTS (INTSTS)

RTC_TICK (TICK)

RTC_TAMSK (TAMSK)

RTC_CAMSK (CAMSK)

RTC_SPRCTL (SPRCTL)

RTC_RWEN (RWEN)

RTC_SPR0 (SPR0)

RTC_SPR1 (SPR1)

RTC_SPR2 (SPR2)

RTC_SPR3 (SPR3)

RTC_SPR4 (SPR4)

RTC_SPR5 (SPR5)

RTC_SPR6 (SPR6)

RTC_SPR7 (SPR7)

RTC_SPR8 (SPR8)

RTC_SPR9 (SPR9)

RTC_SPR10 (SPR10)

RTC_SPR11 (SPR11)

RTC_SPR12 (SPR12)

RTC_SPR13 (SPR13)

RTC_SPR14 (SPR14)

RTC_SPR15 (SPR15)

RTC_FREQADJ (FREQADJ)

RTC_SPR16 (SPR16)

RTC_SPR17 (SPR17)

RTC_SPR18 (SPR18)

RTC_SPR19 (SPR19)

RTC_TIME (TIME)

INIT_ACTIVE : RTC Active Status (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

INIT : RTC Initiation (Write Only)\nWhen RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leave reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.\nThe INIT is a write-only field and read value will be always 0.
bits : 1 - 31 (31 bit)
access : write-only

DAY : 1-Day Calendar Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write

TENDAY : 10-Day Calendar Digit (0~3)
bits : 4 - 5 (2 bit)
access : read-write

MON : 1-Month Calendar Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write

TENMON : 10-Month Calendar Digit (0~1)
bits : 12 - 12 (1 bit)
access : read-write

YEAR : 1-Year Calendar Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write

TENYEAR : 10-Year Calendar Digit (0~9)
bits : 20 - 23 (4 bit)
access : read-write

GAIN : Oscillator Gain Option\nUser can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption.
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE0 : IO Operation Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT0 : IO Output Data
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTLSEL0 : IO Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled, PF.4 pin (X32KO pin) can be used as GPIO function. User can program CTLSEL0 to decide PF.4 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\nPF.4 pin function and I/O status are controlled by OPMODE0[1:0] and DOUT0 after CTLSEL0 is set to 1.\nNote: CTLSEL0 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL0 : IO Pull-up and Pull-down Enable Bits Determine PF.4 I/O pull-up or pull-down. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up / pull-down control register only valid when OPMODE2 set as input tri-state and open-drain mode.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE1 : IO Operation Mode
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT1 : IO Output Data
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTLSEL1 : IO Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled, PF.5 pin (X32KI pin) can be used as GPIO function. User can program CTLSEL1 to decide PF.5 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\nPF.5 pin function and I/O status are controlled by OPMODE1[1:0] and DOUT1 after CTLSEL1 is set to 1.\nNote: CTLSEL1 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL1 : IO Pull-up and Pull-down Enable Bits Determine PF.5 I/O pull-up or pull-down. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up / pull-down control register only valid when OPMODE2 set as input tri-state and open-drain mode.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE2 : IO Operation Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT2 : IO Output Data
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTLSEL2 : IO Pin State Backup Selection\nWhen TAMP0EN is disabled, PF.6 pin (TAMPER0 pin) can be used as GPIO function. User can program CTLSEL2 to decide PF.6 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\nPF.6 pin function and I/O status are controlled by OPMODE2[1:0] and DOUT2 after CTLSEL2 is set to 1.\nNote: CTLSEL2 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL2 : IO Pull-up and Pull-down Enable Bits Determine PF.6 I/O pull-up or pull-down. Note1: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up / pull-down control register only valid when OPMODE2 set as input tri-state and open-drain mode.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE3 : IO Operation Mode
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT3 : IO Output Data
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTLSEL3 : IO Pin State Backup Selection\nWhen TAMP1EN is disabled, PF.7 pin (TAMPER1 pin) can be used as GPIO function. User can program CTLSEL3 to decide PF.7 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0 control register.\nPF.7 pin function and I/O status are controlled by OPMODE3[1:0] and DOUT3 after CTLSEL3 is set to 1.\nNote: CTLSEL3 will automatically be set by hardware to 1 when system power is off and INIT[0](RTC_INIT[0]) is 1.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL3 : IO Pull-up and Pull-down Enable Bits Determine PF.7 I/O pull-up or pull-down. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up / pull-down control register only valid when OPMODE2 set as input tri-state and open-drain mode.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE4 : IO Operation Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT4 : IO Output Data
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTLSEL4 : IO Pin State Backup Selection\nWhen TAMP2EN is disabled, PF.8 pin (TAMPER2 pin) can be used as GPIO function. User can program CTLSEL4 to decide PF.8 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register.\nPF.8 pin function and I/O status are controlled by OPMODE4[1:0] and DOUT4 after CTLSEL4 is set to 1.\nNote: CTLSEL4 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL4 : IO Pull-up and Pull-down Enable Bits Determine PF.8 I/O pull-up or pull-down. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up / pull-down control register only valid when OPMODE2 set as input tri-state and open-drain mode.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE5 : IO Operation Mode
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT5 : IO Output Data
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTLSEL5 : IO Pin State Backup Selection\nWhen TAMP3EN is disabled, PF.9 pin (TAMPER3 pin) can be used as GPIO function. User can program CTLSEL5 to decide PF.9 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register.\nPF.9 pin function and I/O status are controlled by OPMODE5[1:0] and DOUT5 after CTLSEL5 is set to 1.\nNote: CTLSEL5 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL5 : IO Pull-up and Pull-down Enable Bits Determine PF.9 I/O pull-up or pull-down. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up / pull-down control register only valid when OPMODE2 set as input tri-state and open-drain mode.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE6 : IO Operation Mode
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT6 : IO Output Data
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTLSEL6 : IO Pin State Backup Selection\nWhen TAMP4EN is disabled, PF.10 pin (TAMPER4 pin) can be used as GPIO function. User can program CTLSEL6 to decide PF.10 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register.\nPF.10 pin function and I/O status are controlled by OPMODE6[1:0] and DOUT6 after CTLSEL6 is set to 1.\nNote: CTLSEL6 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL6 : IO Pull-up and Pull-down Enable Bits\nDetermine PF.10 I/O pull-up or pull-down.\nNote: Basically, the pull-up control and pull-down control has following behavior limitation.\nThe independent pull-up / pull-down control register only valid when OPMODE2 set as input tri-state and open-drain mode.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE7 : IO Operation Mode
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT7 : IO Output Data
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTLSEL7 : IO Pin State Backup Selection\nWhen TAMP5EN is disabled, PF.11 pin (TAMPER5 pin) can be used as GPIO function. User can program CTLSEL7 to decide PF.11 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL1 control register.\nPF.11 pin function and I/O status are controlled by OPMODE7[1:0] and DOUT7 after CTLSEL7 is set to 1.\nNote: CTLSEL7 will automatically be set by hardware to 1 when system power is off and INIT[0] (RTC_INIT[0]) is 1.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUSEL7 : IO Pull-up and Pull-down Enable Bits Determine PF.11 I/O pull-up or pull-down. Note: Basically, the pull-up control and pull-down control has following behavior limitation. The independent pull-up / pull-down control register only valid when OPMODE2 set as input tri-state and open-drain mode.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDHR : Add 1 Hour
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SUBHR : Subtract 1 Hour
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DSBAK : Daylight Saving Back
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYN1ISS : Dynamic Pair 1 Input Source Select\nThis bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode.\nNote: This bit is effective only when DYNPR1EN (RTC_TAMPCTL[16]) and DYNPR0EN (RTC_TAMPCTL[15]) are set
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYN2ISS : Dynamic Pair 2 Input Source Select\nThis bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode.\nNote: This bit has effect only when DYNPR2EN (RTC_TAMPCTL[24]) and DYNPR0EN (RTC_TAMPCTL[15]) are set
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYNSRC : Dynamic Reference Pattern\nThis fields determine the new reference pattern when current pattern run out in dynamic pair mode.\nNote: After this bit is modified, the SEEDRLD (RTC_TAMPCTL[4]) should be set.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEEDRLD : Reload New Seed for PRNG Engine\nSetting this bit, the tamper configuration will be reload.\nNote: Before this bit is set, the tamper configuration should be set to complete.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYNRATE : Dynamic Change Rate\nThis item is choice the dynamic tamper output change rate.\nNote: After revising this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately.
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP0EN : Tamper0 Detect Enable Bit\nNote1: The reference is RTC-clock. Tamper detector need sync 2 ~ 3 RTC-clock.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP0LV : Tamper 0 Level\nThis bit depends on level attribute of tamper pin for static tamper detection.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP0DBEN : Tamper 0 De-bounce Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP1EN : Tamper 1 Detect Enable Bit\nNote1: The reference is RTC-clock. Tamper detector need sync 2 ~ 3 RTC-clock.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP1LV : Tamper 1 Level\nThis bit depends on level attribute of tamper pin for static tamper detection.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP1DBEN : Tamper 1 De-bounce Enable Bit
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYNPR0EN : Dynamic Pair 0 Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP2EN : Tamper 2 Detect Enable Bit\nNote1: The reference is RTC-clock. Tamper detector need sync 2 ~ 3 RTC-clock.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP2LV : Tamper 2 Level\nThis bit depends on level attribute of tamper pin for static tamper detection.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP2DBEN : Tamper 2 De-bounce Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP3EN : Tamper 3 Detect Enable Bit\nNote1: The reference is RTC-clock. Tamper detector need sync 2 ~ 3 RTC-clock.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP3LV : Tamper 3 Level\nThis bit depends on level attribute of tamper pin for static tamper detection.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP3DBEN : Tamper 3 De-bounce Enable Bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYNPR1EN : Dynamic Pair 1 Enable Bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP4EN : Tamper4 Detect Enable Bit\nNote1: The reference is RTC-clock. Tamper detector need sync 2 ~ 3 RTC-clock.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP4LV : Tamper 4 Level\nThis bit depends on level attribute of tamper pin for static tamper detection.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP4DBEN : Tamper 4 De-bounce Enable Bit
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP5EN : Tamper 5 Detect Enable Bit\nNote: The reference is RTC-clock. Tamper detector need sync 2 ~ 3 RTC-clock.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP5LV : Tamper 5 Level\nThis bit depends on level attribute of tamper pin for static tamper detection.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP5DBEN : Tamper 5 De-bounce Enable Bit
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DYNPR2EN : Dynamic Pair 2 Enable Bit
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEED : Seed Value
bits : 0 - 31 (32 bit)
access : read-write

SEC : 1-Sec Time Digit of TAMPER Time (0~9)
bits : 0 - 3 (4 bit)
access : read-only

TENSEC : 10-Sec Time Digit of TAMPER Time (0~5)
bits : 4 - 6 (3 bit)
access : read-only

MIN : 1-Min Time Digit of TAMPER Time (0~9)
bits : 8 - 11 (4 bit)
access : read-only

TENMIN : 10-Min Time Digit of TAMPER Time (0~5)
bits : 12 - 14 (3 bit)
access : read-only

HR : 1-Hour Time Digit of TAMPER Time (0~9)
bits : 16 - 19 (4 bit)
access : read-only

TENHR : 10-hour Time Digit of TAMPER Time (0~2) \nNote: 24-hour time scale only.
bits : 20 - 21 (2 bit)
access : read-only

DAY : 1-Day Calendar Digit of TAMPER Calendar (0~9)
bits : 0 - 3 (4 bit)
access : read-only

TENDAY : 10-Day Calendar Digit of TAMPER Calendar (0~3)
bits : 4 - 5 (2 bit)
access : read-only

MON : 1-Month Calendar Digit of TAMPER Calendar (0~9)
bits : 8 - 11 (4 bit)
access : read-only

TENMON : 10-Month Calendar Digit of TAMPER Calendar (0~1)
bits : 12 - 12 (1 bit)
access : read-only

YEAR : 1-Year Calendar Digit of TAMPER Calendar (0~9)
bits : 16 - 19 (4 bit)
access : read-only

TENYEAR : 10-Year Calendar Digit of TAMPER Calendar (0~9)
bits : 20 - 23 (4 bit)
access : read-only

_24HEN : 24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WEEKDAY : Day of the Week Register
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEC : 1-Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write

TENSEC : 10-Sec Time Digit of Alarm Setting (0~5)
bits : 4 - 6 (3 bit)
access : read-write

MIN : 1-Min Time Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write

TENMIN : 10-Min Time Digit of Alarm Setting (0~5)
bits : 12 - 14 (3 bit)
access : read-write

HR : 1-Hour Time Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write

TENHR : 10-Hour Time Digit of Alarm Setting (0~2)When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.)
bits : 20 - 21 (2 bit)
access : read-write

DAY : 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write

TENDAY : 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 4 - 5 (2 bit)
access : read-write

MON : 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write

TENMON : 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 12 - 12 (1 bit)
access : read-write

YEAR : 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write

TENYEAR : 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 20 - 23 (4 bit)
access : read-write

LEAPYEAR : Leap Year Indication (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ALMIEN : Alarm Interrupt Enable Bit\nSet ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TICKIEN : Time Tick Interrupt Enable Bit\nSet TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP0IEN : Tamper 0 Interrupt Enable Bit\nSet TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP1IEN : Tamper 1 or Pair 0 Interrupt Enable Bit\nSet TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP2IEN : Tamper 2 Interrupt Enable Bit\nSet TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP3IEN : Tamper 3 or Pair 1 Interrupt Enable Bit\nSet TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP4IEN : Tamper 4 Interrupt Enable Bit\nSet TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP5IEN : Tamper 5 or Pair 2 Interrupt Enable Bit\nSet TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALMIF : RTC Alarm Interrupt Flag\nNote: Write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TICKIF : RTC Time Tick Interrupt Flag\nNote: Write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP0IF : Tamper 0 Interrupt Flag\nThis bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]).\nNote1: Write 1 to clear this bit.\nNote2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP1IF : Tamper 1 or Pair 0 Interrupt Flag\nThis bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated.\nNote1: Write 1 to clear this bit.\nNote2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP2IF : Tamper 2 Interrupt Flag\nThis bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]).\nNote1: Write 1 to clear this bit.\nNote2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP3IF : Tamper 3 or Pair 1 Interrupt Flag\nThis bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated or TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated.\nNote1: Write 1 to clear this bit.\nNote2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP4IF : Tamper 4 Interrupt Flag\nThis bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]).\nNote1: Write 1 to clear this bit.\nNote2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TAMP5IF : Tamper 5 or Pair 2 Interrupt Flag\nThis bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated or TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated.\nNote1: Write 1 to clear this bit.\nNote2: Clear all TAPMxIF will clear RTC_TAMPTIME and RTC_TAMPCAL automatically.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TICK : Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. \nNote: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MSEC : Mask 1-Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 0 (1 bit)
access : read-write

MTENSEC : Mask 10-Sec Time Digit of Alarm Setting (0~5)
bits : 1 - 1 (1 bit)
access : read-write

MMIN : Mask 1-Min Time Digit of Alarm Setting (0~9)
bits : 2 - 2 (1 bit)
access : read-write

MTENMIN : Mask 10-Min Time Digit of Alarm Setting (0~5)
bits : 3 - 3 (1 bit)
access : read-write

MHR : Mask 1-Hour Time Digit of Alarm Setting (0~9)
bits : 4 - 4 (1 bit)
access : read-write

MTENHR : Mask 10-Hour Time Digit of Alarm Setting (0~2)
bits : 5 - 5 (1 bit)
access : read-write

MDAY : Mask 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 0 (1 bit)
access : read-write

MTENDAY : Mask 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 1 - 1 (1 bit)
access : read-write

MMON : Mask 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 2 - 2 (1 bit)
access : read-write

MTENMON : Mask 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 3 - 3 (1 bit)
access : read-write

MYEAR : Mask 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 4 - 4 (1 bit)
access : read-write

MTENYEAR : Mask 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 5 - 5 (1 bit)
access : read-write

SPRRWEN : Spare Register Enable Bit\nNote: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPRCSTS : SPR Clear Flag \nThis bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify tamper event is detected.\nNote1: Write 1 to clear this bit.\nNote2: This bit keeps 1 when RTC_INTSTS[13:8] is not equal to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RWENF : RTC Register Access Enable Flag (Read Only)\nNote: RWENF will be masked to 0 during RTCBUSY is 1, and first turn on RTCCKEN (CLK_APBCLK[1]) also.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RTCBUSY : RTC Write Busy Flag\nThis bit indicates RTC registers are writable or not.\nNote: RTCBUSY flag will be set when execute write RTC register command exceed 6 times within 1120 PCLK cycles.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPARE : Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a tamper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register, user should check REWNF (RTC_RWEN[16]) is enabled.
bits : 0 - 31 (32 bit)
access : read-write