I2C_CTL0

I2C_CLKDIV

I2C_TOCTL

I2C_ADDR1

I2C_ADDR2

I2C_ADDR3

I2C_ADDRMSK0

I2C_ADDRMSK1

I2C_ADDRMSK2

I2C_ADDRMSK3

I2C_WKCTL

I2C_ADDR0

I2C_WKSTS

I2C_CTL1

I2C_STATUS1

I2C_TMCTL

I2C_BUSCTL

I2C_BUSTCTL

I2C_BUSSTS

I2C_PKTSIZE

I2C_PKTCRC

I2C_BUSTOUT

I2C_CLKTOUT

I2C_DAT

I2C_STATUS0

AA : Assert Acknowledge Control
bits : 2 - 2 (1 bit)
access : read-write

SI : I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS0 register, the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.\nFor ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
bits : 3 - 3 (1 bit)
access : read-write

STO : I2C STOP Control\nIn Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically.
bits : 4 - 4 (1 bit)
access : read-write

STA : I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
bits : 5 - 5 (1 bit)
access : read-write

I2CEN : I2C Controller Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN : Enable Interrupt
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIVIDER : I2C Clock Divided \nNote: The minimum value of I2C_CLKDIV is 4.
bits : 0 - 9 (10 bit)
access : read-write

TOIF : Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.\nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

TOCDIV4 : Time-out Counter Input Clock Divided by 4\nWhen enabled, the time-out period is extended 4 times.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOCEN : Time-out Counter Enable Bit\nWhen enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDRMSK : I2C Address Mask\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.\nNote: The wake-up function can not use address mask.
bits : 1 - 10 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN : I2C Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NHDBUSEN : I2C No Hold BUS Enable Bit Note: The I2C controller could respond when WKIF event is not clear, it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GC : General Call Function
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDR : I2C Address \nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.\nNote: When software set 10'h000, the address can not be used.
bits : 1 - 10 (10 bit)
access : read-write

WKIF : I2C Wake-up Flag\nWhen chip is woken up from Power-down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

WKAKDONE : Wakeup Address Frame Acknowledge Bit Done\nNote: This bit can't release WKIF. Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WRSTSWK : Read/Write Status Bit in Address Wakeup Frame\nNote: This bit will be cleared when software can write 1 to WKAKDONE bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXPDMAEN : PDMA Transmit Channel Available
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXPDMAEN : PDMA Receive Channel Available
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMARST : PDMA Reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMASTR : PDMA Stretch Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDR10EN : Address 10-bit Function Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMAT0 : I2C Address 0 Match Status\nWhen address 0 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

ADMAT1 : I2C Address 1 Match Status\nWhen address 1 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

ADMAT2 : I2C Address 2 Match Status\nWhen address 2 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

ADMAT3 : I2C Address 3 Match Status\nWhen address 3 is matched, hardware will inform which address used. This bit will set to 1, and software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write

ONBUSY : On Bus Busy (Read Only)\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

STCTL : Setup Time Configure Control\nThis field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.\nNote: Setup time setting should not make SCL output less than three PCLKs.
bits : 0 - 8 (9 bit)
access : read-write

HTCTL : Hold Time Configure Control \nThis field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode.
bits : 16 - 24 (9 bit)
access : read-write

ACKMEN : Acknowledge Control by Manual\nIn order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PECEN : Packet Error Checking Calculation Enable Bit\nNote: When I2C enter powerdown mode, the bit should be enabled after wake-up if needed PEC calculation.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BMDEN : Bus Management Device Default Address Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BMHEN : Bus Management Host Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALERTEN : Bus Management Alert Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCTLOSTS : Suspend/Control Data Output Status
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCTLOEN : Suspend or Control Pin Output Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSEN : BUS Enable Bit\nNote: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PECTXEN : Packet Error Checking Byte Transmission/Reception
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIDLE : Timer Check in Idle State\nThe BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.\nNote: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PECCLR : PEC Clear at Repeat Start\nThe calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACKM9SI : Acknowledge Manual Enable Extra SI Interrupt
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BCDIEN : Packet Error Checking Byte Count Done Interrupt Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PECDIEN : Packet Error Checking Byte Transfer Done Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSTOEN : Bus Time Out Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKTOEN : Cumulative Clock Low Time Out Enable Bit\nFor Master, it calculates the period from START to ACK\nFor Slave, it calculates the period from START to STOP
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSTOIEN : Time-out Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKTOIEN : Extended Clock Time Out Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TORSTEN : Time Out Reset Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSY : Bus Busy\nIndicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BCDONE : Byte Count Transmission/Receive Done \nNote: Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PECERR : PEC Error in Reception \nNote: Software can write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALERT : SMBus Alert Status \nNote: 1. The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCTLDIN : Bus Suspend or Control Signal Input Status
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSTO : Bus Time-out Status In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred. Note: Software can write 1 to clear this bit.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKTO : Clock Low Cumulate Time-out Status \nNote: Software can write 1 to clear this bit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PECDONE : PEC Byte Transmission/Receive Done \nNote: Software can write 1 to clear this bit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLDSIZE : Transfer Byte Number\nThe transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.\nNote: The byte number counting includes address, command code, and data frame.
bits : 0 - 8 (9 bit)
access : read-write

PECCRC : Packet Error Checking Byte Value
bits : 0 - 7 (8 bit)
access : read-only

BUSTO : Bus Management Time-out Value\nIndicates the bus time-out value in bus is IDLE or SCLK low.\nNote: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.
bits : 0 - 7 (8 bit)
access : read-write

CLKTO : Bus Clock Low Timer\nThe field is used to configure the cumulative clock extension time-out.\nNote: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set.
bits : 0 - 7 (8 bit)
access : read-write

DAT : I2C Data \nBit [7:0] is located with the 8-bit transferred/received data of I2C serial port.
bits : 0 - 7 (8 bit)
access : read-write

STATUS : I2C Status
bits : 0 - 7 (8 bit)
access : read-only