\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x44 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
A/D Data Register
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSLT : A/D Conversion Result\nThis field contains conversion result of ADC.
bits : 0 - 9 (10 bit)
access : read-only
OVERRUN : Over Run Flag\nIf converted data in RSLT[9:0] has not been read before the new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after the ADDR register is read.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RSLT[9:0] is recent conversion result
#1 : 1
Data in RSLT[9:0] overwritten
End of enumeration elements list.
VALID : Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADDR register is read.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RSLT[9:0] bits not valid
#1 : 1
Data in RSLT[9:0] bits valid
End of enumeration elements list.
A/D Control Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADEN : A/D Converter Enable\nBefore starting the A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
ADIE : A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D interrupt function Disabled
#1 : 1
A/D interrupt function Enabled
End of enumeration elements list.
TRGS : Hardware Trigger Source\nSoftware should disable TRGEN and ADST before change TRGS.\nIn hardware trigger mode, the ADST bit is set by the external trigger from STADC.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
A/D conversion is started by external STADC pin
#11 : 3
A/D conversion is started by PWM trigger
End of enumeration elements list.
TRGCOND : External Trigger Condition\nThis bit decides whether the external pin STADC trigger event is falling or raising edge. The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigger.\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling edge
#1 : 1
Raising edge
End of enumeration elements list.
TRGEN : External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin.\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
ADST : A/D Conversion Start\nADST bit can be set to 1 from two sources: software and external pin STADC. ADST will be cleared to 0 by hardware automatically.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion stopped and A/D converter entered idle state
#1 : 1
Conversion start
End of enumeration elements list.
A/D Channel Enable Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN0 : Analog Input Channel 0 Enable\nNote: If software enables more than one channel, the channel with the lowest number will be selected and the other enabled channels will be ignored. That means channel 0 is the highest priority.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN1 : Analog Input Channel 1 Enable\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN2 : Analog Input Channel 2 Enable\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN3 : Analog Input Channel 3 Enable\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN4 : Analog Input Channel 4 Enable\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN5 : Analog Input Channel 5 Enable\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN6 : Analog Input Channel 6 Enable\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN7 : Analog Input Channel 7 Enable\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PRESEL : Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7, the ADC clock rate needs to be limited to lower than 300 kHz.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Input Channel 7
#1 : 1
Band-gap (VBG) Analog Input
End of enumeration elements list.
A/D Compare Register 0
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPEN : Compare Enable\nSet 1 to this bit to enable comparing CMPD[9:0] with specified channel conversion results when converted data is loaded into the ADDR register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function Disabled
#1 : 1
Compare function Enabled
End of enumeration elements list.
CMPIE : Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function interrupt Disabled
#1 : 1
Compare function interrupt Enabled
End of enumeration elements list.
CMPCOND : Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the compare condition as that when a 10-bit A/D conversion result is less than the 10-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one
#1 : 1
Set the compare condition as that when a 10-bit A/D conversion result is greater or equal to the 10-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one
End of enumeration elements list.
CMPCH : Compare Channel Selection\n
bits : 3 - 5 (3 bit)
access : read-write
CMPMATCNT : Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
bits : 8 - 11 (4 bit)
access : read-write
CMPD : Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel.
bits : 16 - 25 (10 bit)
access : read-write
A/D Compare Register 1
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Status Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADF : A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 When A/D conversion ends.\nSoftware can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write
CMPF0 : Compare Flag #0\nWhen the selected channel A/D conversion result meets the setting condition in ADCMPR0, this bit is set to 1. Software can write 1 to clear this bit to zero.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADDR does not meet the ADCMPR0 setting
#1 : 1
Conversion result in ADDR meets the ADCMPR0 setting
End of enumeration elements list.
CMPF1 : Compare Flag #1\nWhen the selected channel A/D conversion result meets the setting condition in ADCMPR1, this bit is set to 1. Software can write 1 to clear this bit to zero.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADDR does not meet the ADCMPR1 setting
#1 : 1
Conversion result in ADDR meets the ADCMPR1 setting
End of enumeration elements list.
BUSY : BUSY/IDLE\nThis bit is mirror of as ADST bit in ADCR.\nIt is read only.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D converter is in idle state
#1 : 1
A/D converter is busy at conversion
End of enumeration elements list.
CHANNEL : Current Conversion Channel\nIt is read only.
bits : 4 - 6 (3 bit)
access : read-write
VALID : Data Valid Flag\nIt is a mirror of VALID bit in ADDR.
bits : 8 - 8 (1 bit)
access : read-write
OVERRUN : Over Run Flag\nIt is a mirror to OVERRUN bit in ADDR.
bits : 16 - 16 (1 bit)
access : read-write
A/D Trigger Delay Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTDT : PWM Trigger Delay Timer\nSet this field will delay ADC start conversion time after PWM trigger is coming.\nPWM trigger delay time is (4 * PTDT) * system clock
bits : 0 - 7 (8 bit)
access : read-write
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