\n
address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
ISP Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPEN : ISP Enable\nISP function enable bit. Set this bit to enable ISP function.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP function Disabled
#1 : 1
ISP function Enabled
End of enumeration elements list.
BS : Boot Selection
Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as MCU booting status flag, which can be used to check where MCU booted from. This bit is initiated with the inversed value of CBS in Config0 after power-on reset It keeps the same value at other reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Boot from APROM
#1 : 1
Boot from LDROM
End of enumeration elements list.
CFGUEN : Enable Config-bits Update by ISP\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable ISP can update config-bits
#1 : 1
Enable ISP can update config-bits
End of enumeration elements list.
LDUEN : LDROM Update Enable\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
LDROM cannot be updated
#1 : 1
LDROM can be updated when the MCU runs in APROM
End of enumeration elements list.
ISPFF : ISP Fail Flag\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself.\n(2) LDROM writes to itself.\n(3) CONFIG is erased/programmed when the MCU is running in APROM.\n(4) Destination address is illegal, such as over an available range.\nSoftware can write 1 to clear this bit.
bits : 6 - 6 (1 bit)
access : read-write
SWRST : Software Reset\nWriting 1 to this bit to start software reset.\nIt is cleared by hardware after reset is finished.
bits : 7 - 7 (1 bit)
access : read-write
PT : Flash Program Time\n
bits : 8 - 10 (3 bit)
access : read-write
ET : Flash Erase Time\n
bits : 12 - 14 (3 bit)
access : read-write
ISP Trigger Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPGO : ISP Start Trigger
Write 1 to start ISP operation this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP operation finished
#1 : 1
ISP on going
End of enumeration elements list.
Data Flash Start Address
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DFBA : Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nThe data flash start address is defined by user. Since on chip flash erase unit is 512 bytes, it is mandatory to keep bit 8-0 as 0.
bits : 0 - 31 (32 bit)
access : read-only
ISP Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPADR : ISP Address\nThe NuMicro Mini51TM series supports word program only. ISPADR[1:0] must be kept 00 for ISP operation.
bits : 0 - 31 (32 bit)
access : read-write
ISP Data Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT : ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write
ISP Command Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FOEN_FCEN_FCTRL : ISP Command\n
bits : 0 - 5 (6 bit)
access : read-write
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