PDID

REGWRPROT

BODCR

P0_MFP

P1_MFP

P2_MFP

P3_MFP

RSTSRC

P4_MFP

P5_MFP

IPRSTC1

IRCTRIMCTL

IRCTRIMIEN

IRCTRIMINT

IPRSTC2

PDID : Product Device Identification Number This register reflects the device part number code. Software can read this register to identify which device is used. For example, the MINI51LDE PDID code is 0x20205100 .
bits : 0 - 31 (32 bit)
access : read-only

REGPROTDIS : Register Write-protection Disable Index (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REGWRPROT : Register Write-protection Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 0x59, 0x16, 0x88 to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write.
bits : 0 - 7 (8 bit)
access : write-only

BOD_VL_EXT : Brown-out Detector Selection Extension (Initiated Write-protected Bit)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_VL : Brown-out Detector Threshold Voltage Selection (Initiated Write-protected Bit)
bits : 1 - 2 (2 bit)
access : read-write

BOD_RSTEN : Brown-out Reset Enable Control (Initiated And Write-protected Bit)\nThe default value is set by flash controller user configuration register config0 bit[20].\nWhen the BOD_EN is enabled and the interrupt is asserted, the interrupt will be kept till the BOD_EN is set to 0. The interrupt for CPU can be blocked by disabling the NVIC in CPU for BOD interrupt or disable the interrupt source by disabling the BOD_EN and then re-enabling the BOD_EN function if the BOD function is required.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_INTF : Brown-out Detector Interrupt Flag\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_LPM : Brown-out Detector Low Power Mode (Write Protect)\nThe BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1uA but slow the BOD response.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_OUT : Brown-out Detector Output State\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P0_MFP : P0 Multiple Function Selection\nThe pin function of P0 depends on P0_MFP and P0_ALT.\nRefer to P0_ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

P0_ALT0 : P0.0 Alternate Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

P0_ALT1 : P0.1 Alternate Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

P0_ALT4 : P0.4 Alternate Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

P0_ALT5 : P0.5 Alternate Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

P0_ALT6 : P0.6 Alternate Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

P0_ALT7 : P0.7 Alternate Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

P0_TYPE : P0[7:0] TTL Or Schmitt Trigger Function Enable Control\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P1_MFP : P1 Multiple Function Selection\nThe pin function of P1 depends on P1_MFP and P1_ALT.\nRefer to P1_ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

P1_ALT0 : P1.0 Alternate Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

P1_ALT2 : P1.2 Alternate Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

P1_ALT3 : P1.3 Alternate Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

P1_ALT4 : P1.4 Alternate Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

P1_ALT5 : P1.5 Alternate Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

P1_TYPE : P1[7:0] TTL Or Schmitt Trigger Function Enable Control\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P2_MFP : P2 Multiple Function Selection\nThe pin function of P2 depends on P2_MFP and P2_ALT.\nRefer to P2_ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

P2_ALT2 : P2.2 Alternate Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

P2_ALT3 : P2.3 Alternate Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

P2_ALT4 : P2.4 Alternate Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

P2_ALT5 : P2.5 Alternate Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

P2_ALT6 : P2.6 Alternate Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

P2_TYPE : P2[7:0] TTL Or Schmitt Trigger Function Enable Control\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P3_MFP : P3 Multiple Function Selection\nThe pin function of P3 depends on P3_MFP and P3_ALT.\nRefer to P3_ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

P3_ALT0 : P3.0 Alternate Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

P3_ALT1 : P3.1 Alternate Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

P3_ALT2 : P3.2 Alternate Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

P3_ALT4 : P3.4 Alternate Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

P3_ALT5 : P3.5 Alternate Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

P3_ALT6 : P3.6 Alternate Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

P3_TYPE : P3[7:0] TTL Or Schmitt Trigger Function Enable Control\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P32CPP1 : P3.2 Alternate Function Selection Extension\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_POR : Power-on Reset Flag The RSTS_POR flag is set by the reset signal , which is from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]), to indicate the previous reset source. Note: Software can write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_RESET : Reset Pin Reset Flag The RSTS_RESET flag is set by the reset signal from the /RESET pin to indicate the previous reset source. Note: Software can write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_WDT : Watchdog Reset Flag The RSTS_WDT flag is set by the reset signal from the Watchdog timer to indicate the previous reset source. Note: Software can write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_BOD : Brown-out Detector Reset Flag The RSTS_BOD flag is set by the reset signal from the Brown-out Detector to indicate the previous reset source. Note: Software can write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_MCU : MCU Reset Flag The RSTS_MCU flag is set by the reset signal from the Cortex-M0 core to indicate the previous reset source. Note: Software can write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_CPU : CPU Reset Flag\nThe RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 core and Flash memory controller (FMC).\nNote: Software can write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P4_MFP : P4 Multiple Function Selection\nThe pin function of P4 depends on P4_MFP and P4_ALT.\nRefer to P4_ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

P4_ALT6 : P4.6 Alternate Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

P4_ALT7 : P4.7 Alternate Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

P4_TYPE : P4[7:0] TTL Or Schmitt Trigger Function Enable Control\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P5_MFP : P5 Multiple Function Selection\nThe pin function of P5 depends on P5_MFP and P5_ALT.\nRefer to P5_ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

P5_ALT0 : P5.0 Alternate Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

P5_ALT1 : P5.1 Alternate Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

P5_ALT2 : P5.2 Alternate Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

P5_ALT3 : P5.3 Alternate Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

P5_ALT4 : P5.4 Alternate Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

P5_ALT5 : P5.5 Alternate Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

P5_TYPE : P5[7:0] TTL Or Schmitt Trigger Function Enable Control\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHIP_RST : CHIP One-shot Reset (Write Protect)\nSetting this bit will reset the CHIP, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is the same as the POR reset, and all the chip module is reset and the chip settings from flash are also reloaded.\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA + 0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPU_RST : CPU Kernel Reset\nSetting this bit will reset the CPU kernel, and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA + 0x100.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIM_SEL : Trim Frequency Selection\nThis bit is to enable the HIRC auto trim.\nWhen setting this bit to 1, the HIRC auto trim function will trim HIRC to 22.1184 MHz automatically based on the LXT reference clock.\nDuring auto trim operation, if LXT clock error is detected or trim retry limitation count reached, this field will be cleared to 0 automatically.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIM_LOOP : Trim Calculation Loop\nThis field defines that trim value calculation is based on how many LXT clocks in.\nFor example, if TRIM_LOOP is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 LXT clock.\n
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIM_RETRY_CNT : Trim Value Update Limitation Count\n
bits : 6 - 7 (2 bit)
access : read-write

TRIM_FAIL_IEN : Trim Failure Interrupt Enable Control\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count is reached and HIRC frequency is still not locked on target frequency set by TRIM_SEL.\nIf this bit is high and TRIM_FAIL_INT is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count is reached.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

_32K_ERR_IEN : LXT Clock Error Interrupt Enable Control\nThis bit controls if CPU could get an interrupt while LXT clock is inaccurate during auto trim operation.\nIf this bit is high, and 32K_ERR_INT is set during auto trim operation, an interrupt will be triggered to notify the LXT clock frequency is inaccurate.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQ_LOCK : HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency locked in 22.1184 MHz.\nThis is a read only status bit and doesn't trigger any interrupt.
bits : 0 - 0 (1 bit)
access : read-write

TRIM_FAIL_INT : Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 0 by hardware automatically.\nIf this bit is set and TRIM_FAIL_IEN is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Software can write 1 to clear this bit to 0.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

_32K_ERR_INT : LXT Clock Error Interrupt Status\nThis bit indicates that LXT clock frequency is inaccuracy. Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 0 by hardware automatically.\nIf this bit is set and 32K_ERR_IEN is high, an interrupt will be triggered to notify the LXT clock frequency is inaccuracy. Software can write 1 to clear this bit to 0.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIO_RST : GPIO (P0~P5) Controller Reset\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_RST : Timer0 Controller Reset\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1_RST : Timer1 Controller Reset\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C_RST : I2C Controller Reset\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI_RST : SPI Controller Reset\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART_RST : UART Controller Reset\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM_RST : PWM Controller Reset\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP_RST : ACMP Controller Reset\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC_RST : ADC Controller Reset\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.