\n

GPIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x200 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x80 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x140 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x210 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x228 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x248 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x260 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x270 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x298 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

P0_PMD

P0_PIN

P4_PMD

P4_OFFD

P4_DOUT

P4_DMASK

P4_PIN

P4_DBEN

P4_IMD

P4_IEN

P4_ISRC

P0_DBEN

P5_PMD

P5_OFFD

P5_DOUT

P5_DMASK

P5_PIN

P5_DBEN

P5_IMD

P5_IEN

P5_ISRC

P0_IMD

DBNCECON

P0_IEN

P0_ISRC

P00_PDIO

P01_PDIO

P04_PDIO

P05_PDIO

P06_PDIO

P07_PDIO

P10_PDIO

P12_PDIO

P13_PDIO

P14_PDIO

P15_PDIO

P22_PDIO

P23_PDIO

P24_PDIO

P25_PDIO

P26_PDIO

P30_PDIO

P31_PDIO

P32_PDIO

P34_PDIO

P35_PDIO

P36_PDIO

P46_PDIO

P47_PDIO

P50_PDIO

P51_PDIO

P52_PDIO

P53_PDIO

P54_PDIO

P55_PDIO

P0_OFFD

P1_PMD

P1_OFFD

P1_DOUT

P1_DMASK

P1_PIN

P1_DBEN

P1_IMD

P1_IEN

P1_ISRC

P0_DOUT

P2_PMD

P2_OFFD

P2_DOUT

P2_DMASK

P2_PIN

P2_DBEN

P2_IMD

P2_IEN

P2_ISRC

P0_DMASK

P3_PMD

P3_OFFD

P3_DOUT

P3_DMASK

P3_PIN

P3_DBEN

P3_IMD

P3_IEN

P3_ISRC


P0_PMD

P0 I/O Mode Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_PMD P0_PMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7

PMD0 : Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12], [3:2] are reserved.\nP2_PMD[15:14], [3:0] are reserved.\nP3_PMD[15:14], [7:6] are reserved.\nP4_PMD[11:0] are reserved.\nP5_PMD[15:12] are reserved.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

PMD1 : Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12], [3:2] are reserved.\nP2_PMD[15:14], [3:0] are reserved.\nP3_PMD[15:14], [7:6] are reserved.\nP4_PMD[11:0] are reserved.\nP5_PMD[15:12] are reserved.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

PMD2 : Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12], [3:2] are reserved.\nP2_PMD[15:14], [3:0] are reserved.\nP3_PMD[15:14], [7:6] are reserved.\nP4_PMD[11:0] are reserved.\nP5_PMD[15:12] are reserved.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

PMD3 : Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12], [3:2] are reserved.\nP2_PMD[15:14], [3:0] are reserved.\nP3_PMD[15:14], [7:6] are reserved.\nP4_PMD[11:0] are reserved.\nP5_PMD[15:12] are reserved.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

PMD4 : Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12], [3:2] are reserved.\nP2_PMD[15:14], [3:0] are reserved.\nP3_PMD[15:14], [7:6] are reserved.\nP4_PMD[11:0] are reserved.\nP5_PMD[15:12] are reserved.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

PMD5 : Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12], [3:2] are reserved.\nP2_PMD[15:14], [3:0] are reserved.\nP3_PMD[15:14], [7:6] are reserved.\nP4_PMD[11:0] are reserved.\nP5_PMD[15:12] are reserved.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

PMD6 : Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12], [3:2] are reserved.\nP2_PMD[15:14], [3:0] are reserved.\nP3_PMD[15:14], [7:6] are reserved.\nP4_PMD[11:0] are reserved.\nP5_PMD[15:12] are reserved.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.

PMD7 : Port 0-5 I/O Pin [N] Mode Control\nDetermine each I/O mode of Px.n pin. Default mode is controlled by CIOINI (CONFIG0[10]).\nNote2:\nP0_PMD[7:4] are reserved.\nP1_PMD[15:12], [3:2] are reserved.\nP2_PMD[15:14], [3:0] are reserved.\nP3_PMD[15:14], [7:6] are reserved.\nP4_PMD[11:0] are reserved.\nP5_PMD[15:12] are reserved.
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 0

Px.n is in Input mode

#01 : 1

Px.n is in Push-pull Output mode

#10 : 2

Px.n is in Open-drain Output mode

#11 : 3

Px.n is in Quasi-bidirectional mode

End of enumeration elements list.


P0_PIN

P0 Pin Value
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

P0_PIN P0_PIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN

PIN : Port 0-5 Pin [N] Pin Value Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low. Note2: P0_PIN[3:2] are reserved. P1_PIN[7:6], [1] are reserved. P2_PIN[7], [1:0] are reserved. P3_PIN[7], [3] are reserved. P4_PIN[5:0] are reserved. P5_PIN[7:6] are reserved.
bits : 0 - 7 (8 bit)
access : read-only


P4_PMD

P4 I/O Mode Control
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_PMD P4_PMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P4_OFFD

P4 Digital Input Path Disable Control
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_OFFD P4_OFFD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P4_DOUT

P4 Data Output Value
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_DOUT P4_DOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P4_DMASK

P4 Data Output Write Mask
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_DMASK P4_DMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P4_PIN

P4 Pin Value
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_PIN P4_PIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P4_DBEN

P4 De-bounce Enable Control
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_DBEN P4_DBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P4_IMD

P4 Interrupt Mode Control
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_IMD P4_IMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P4_IEN

P4 Interrupt Enable Control
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_IEN P4_IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P4_ISRC

P4 Interrupt Source Flag
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P4_ISRC P4_ISRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P0_DBEN

P0 De-bounce Enable Control
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_DBEN P0_DBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBEN

DBEN : Port 0-5 Pin [N] Input Signal De-bounce Enable Control\nDBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle period is controlled by DBNCECON[3:0].\nNote2: If Px.n pin is chosen as Power-down wake-up source, user should be disable the de-bounce function before entering Power-down mode to avoid the second interrupt event occurred after system woken up caused by the Px.n de-bounce function.\nNote3:\nP0_DBEN[3:2] are reserved.\nP1_DBEN[7:6], [1] are reserved.\nP2_DBEN[7], [1:0] are reserved.\nP3_DBEN[7], [3] are reserved.\nP4_DBEN[5:0] are reserved.\nP5_DBEN[7:6] are reserved.
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0 : 0

Px.n de-bounce function Disabled

1 : 1

Px.n de-bounce function Enabled

End of enumeration elements list.


P5_PMD

P5 I/O Mode Control
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_PMD P5_PMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P5_OFFD

P5 Digital Input Path Disable Control
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_OFFD P5_OFFD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P5_DOUT

P5 Data Output Value
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_DOUT P5_DOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P5_DMASK

P5 Data Output Write Mask
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_DMASK P5_DMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P5_PIN

P5 Pin Value
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_PIN P5_PIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P5_DBEN

P5 De-bounce Enable Control
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_DBEN P5_DBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P5_IMD

P5 Interrupt Mode Control
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_IMD P5_IMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P5_IEN

P5 Interrupt Enable Control
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_IEN P5_IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P5_ISRC

P5 Interrupt Source Flag
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P5_ISRC P5_ISRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P0_IMD

P0 Interrupt Mode Control
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_IMD P0_IMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMD

IMD : Port 0-5 Pin [N] Edge Or Level Detection Interrupt Mode Control\nIMD[n] bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote2:\nP0_IMD[3:2] are reserved.\nP1_IMD[7:6], [1] are reserved.\nP2_IMD[7], [1:0] are reserved.\nP3_IMD[7], [3] are reserved.\nP4_IMD[5:0] are reserved.\nP5_IMD[7:6] are reserved.
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0 : 0

Edge trigger interrupt

1 : 1

Level trigger interrupt

End of enumeration elements list.


DBNCECON

Interrupt De-bounce Control
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBNCECON DBNCECON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBCLKSEL DBCLKSRC ICLK_ON

DBCLKSEL : De-bounce Sampling Cycle Selection\n
bits : 0 - 3 (4 bit)
access : read-write

DBCLKSRC : De-bounce Counter Clock Source Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

De-bounce counter clock source is the HCLK

#1 : 1

De-bounce counter clock source is the 10 kHz internal low speed oscillator

End of enumeration elements list.

ICLK_ON : Interrupt Clock On Mode\nNote: It is recommended to turn off this bit to save system power if no special application concern.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge detection circuit is active only if I/O pin corresponding Px_IEN bit is set to 1

#1 : 1

All I/O pins edge detection circuit is always active after reset

End of enumeration elements list.


P0_IEN

P0 Interrupt Enable Control
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_IEN P0_IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IF_EN IR_EN

IF_EN : Port 0-5 Pin [N] Interrupt Enabled By Input Falling Edge Or Input Level Low\nIF_EN[n] is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IF_EB[n] bit to 1:\nIf the interrupt is level trigger (IMD[n] is 1), the input Px.n pin will generate the interrupt while this pin state is at low level.\nIf the interrupt is edge mode trigger (IMD[n] is 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.\nNote2:\nP0_IEN[19:18], [3:2] are reserved.\nP1_IEN[23:22], [17], [7:6], [1] are reserved.\nP2_IEN[23], [17:16], [7], [1:0] are reserved.\nP3_IEN[23], [19], [7], [3] are reserved.\nP4_IEN[21:16], [5:0] are reserved.\nP5_IEN[23:22], [7:6] are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Px.n low level or high to low interrupt Disabled

#1 : 1

Px.n low level or high to low interrupt Enabled

End of enumeration elements list.

IR_EN : Port 0-5 Pin [N] Interrupt Enabled By Input Rising Edge Or Input Level High\nIR_EN[n] bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.\nWhen setting the IR_EN[n] bit to 1:\nIf the interrupt is level trigger (IMD[n] is 1), the input Px.n pin will generate the interrupt while this pin state is at high level.\nIf the interrupt is edge trigger (IMD[n] is 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0 : 0

Px.n level high or low to high interrupt Disabled

1 : 1

Px.n level high or low to high interrupt Enabled

End of enumeration elements list.


P0_ISRC

P0 Interrupt Source Flag
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_ISRC P0_ISRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISRC

ISRC : Port 0-5 Pin [N] Interrupt Source Flag\nWrite :\nNote2:\nP0_ISRC[3:2] are reserved.\nP1_ISRC[7:6], [1] are reserved.\nP2_ISRC[7], [1:0] are reserved.\nP3_ISRC[7], [3] are reserved.\nP4_ISRC[5:0] are reserved.\nP5_ISRC[7:6] are reserved.
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0 : 0

No action.\nNo interrupt at Px.n

1 : 1

Clear the corresponding pending interrupt.\nPx.n generates an interrupt

End of enumeration elements list.


P00_PDIO

GPIO P0.0 Pin Data Input/Output
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P00_PDIO P00_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P_PDIO

P_PDIO : GPIO Px.N Pin Data Iutput/Output\nWriting this bit can control one GPIO pin output value.\nNote2: The writing operation will not be affected by register Px_DMASK[n].
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Corresponding GPIO pin set to low.\nCorresponding GPIO pin status is low

#1 : 1

Corresponding GPIO pin set to high.\nCorresponding GPIO pin status is high

End of enumeration elements list.


P01_PDIO

GPIO P0.1 Pin Data Input/Output
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P01_PDIO P01_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P04_PDIO

GPIO P0.4 Pin Data Input/Output
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P04_PDIO P04_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P05_PDIO

GPIO P0.5 Pin Data Input/Output
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P05_PDIO P05_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P06_PDIO

GPIO P0.6 Pin Data Input/Output
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P06_PDIO P06_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P07_PDIO

GPIO P0.7 Pin Data Input/Output
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P07_PDIO P07_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P10_PDIO

GPIO P1.0 Pin Data Input/Output
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P10_PDIO P10_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P12_PDIO

GPIO P1.2 Pin Data Input/Output
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P12_PDIO P12_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P13_PDIO

GPIO P1.3 Pin Data Input/Output
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P13_PDIO P13_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P14_PDIO

GPIO P1.4 Pin Data Input/Output
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P14_PDIO P14_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P15_PDIO

GPIO P1.5 Pin Data Input/Output
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P15_PDIO P15_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P22_PDIO

GPIO P2.2 Pin Data Input/Output
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P22_PDIO P22_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P23_PDIO

GPIO P2.3 Pin Data Input/Output
address_offset : 0x24C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P23_PDIO P23_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P24_PDIO

GPIO P2.4 Pin Data Input/Output
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P24_PDIO P24_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P25_PDIO

GPIO P2.5 Pin Data Input/Output
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P25_PDIO P25_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P26_PDIO

GPIO P2.6 Pin Data Input/Output
address_offset : 0x258 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P26_PDIO P26_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P30_PDIO

GPIO P3.0 Pin Data Input/Output
address_offset : 0x260 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P30_PDIO P30_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P31_PDIO

GPIO P3.1 Pin Data Input/Output
address_offset : 0x264 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P31_PDIO P31_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P32_PDIO

GPIO P3.2 Pin Data Input/Output
address_offset : 0x268 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P32_PDIO P32_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P34_PDIO

GPIO P3.4 Pin Data Input/Output
address_offset : 0x270 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P34_PDIO P34_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P35_PDIO

GPIO P3.5 Pin Data Input/Output
address_offset : 0x274 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P35_PDIO P35_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P36_PDIO

GPIO P3.6 Pin Data Input/Output
address_offset : 0x278 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P36_PDIO P36_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P46_PDIO

GPIO P4.6 Pin Data Input/Output
address_offset : 0x298 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P46_PDIO P46_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P47_PDIO

GPIO P4.7 Pin Data Input/Output
address_offset : 0x29C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P47_PDIO P47_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P50_PDIO

GPIO P5.0 Pin Data Input/Output
address_offset : 0x2A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P50_PDIO P50_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P51_PDIO

GPIO P5.1 Pin Data Input/Output
address_offset : 0x2A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P51_PDIO P51_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P52_PDIO

GPIO P5.2 Pin Data Input/Output
address_offset : 0x2A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P52_PDIO P52_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P53_PDIO

GPIO P5.3 Pin Data Input/Output
address_offset : 0x2AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P53_PDIO P53_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P54_PDIO

GPIO P5.4 Pin Data Input/Output
address_offset : 0x2B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P54_PDIO P54_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P55_PDIO

GPIO P5.5 Pin Data Input/Output
address_offset : 0x2B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P55_PDIO P55_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P0_OFFD

P0 Digital Input Path Disable Control
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_OFFD P0_OFFD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFD

OFFD : Port 0-5 Pin [N] Digital Input Path Disable Control\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0 : 0

Px.n digital input path Enabled

1 : 1

Px.n digital input path Disabled (digital input tied to low)

End of enumeration elements list.


P1_PMD

P1 I/O Mode Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_PMD P1_PMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P1_OFFD

P1 Digital Input Path Disable Control
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_OFFD P1_OFFD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P1_DOUT

P1 Data Output Value
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_DOUT P1_DOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P1_DMASK

P1 Data Output Write Mask
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_DMASK P1_DMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P1_PIN

P1 Pin Value
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_PIN P1_PIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P1_DBEN

P1 De-bounce Enable Control
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_DBEN P1_DBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P1_IMD

P1 Interrupt Mode Control
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_IMD P1_IMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P1_IEN

P1 Interrupt Enable Control
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_IEN P1_IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P1_ISRC

P1 Interrupt Source Flag
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P1_ISRC P1_ISRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P0_DOUT

P0 Data Output Value
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_DOUT P0_DOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOUT

DOUT : Port 0-5 Pin [N] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output and Quasi-bidirectional mode.\nNote2:\nP0_DOUT[3:2] are reserved.\nP1_DOUT[7:6], [1] are reserved.\nP2_DOUT[7], [1:0] are reserved.\nP3_DOUT[7], [3] are reserved.\nP4_DOUT[5:0] are reserved.\nP5_DOUT[7:6] are reserved.
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0 : 0

Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode

1 : 1

Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode

End of enumeration elements list.


P2_PMD

P2 I/O Mode Control
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_PMD P2_PMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P2_OFFD

P2 Digital Input Path Disable Control
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_OFFD P2_OFFD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P2_DOUT

P2 Data Output Value
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_DOUT P2_DOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P2_DMASK

P2 Data Output Write Mask
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_DMASK P2_DMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P2_PIN

P2 Pin Value
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_PIN P2_PIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P2_DBEN

P2 De-bounce Enable Control
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_DBEN P2_DBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P2_IMD

P2 Interrupt Mode Control
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_IMD P2_IMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P2_IEN

P2 Interrupt Enable Control
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_IEN P2_IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P2_ISRC

P2 Interrupt Source Flag
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P2_ISRC P2_ISRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P0_DMASK

P0 Data Output Write Mask
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P0_DMASK P0_DMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMASK

DMASK : Port 0-5 Pin [N] Data Output Write Mask\nThese bits are used to protect the corresponding Px_DOUT[n] bit. When the DMASK[n] bit is set to 1, the corresponding Px_DOUT[n] bit is protected. If the write signal is masked, writing data to the protect bit is ignored.\nNote2: This function only protects the corresponding Px_DOUT[n] bit, and will not protect the corresponding Pxn_PDIO bit.\nNote3:\nP0_DMASK[3:2] are reserved.\nP1_DMASK[7:6], [1] are reserved.\nP2_DMASK[7], [1:0] are reserved.\nP3_DMASK[7], [3] are reserved.\nP4_DMASK[5:0] are reserved.\nP5_DMASK[7:6] are reserved.
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0 : 0

Corresponding Px_DOUT[n] bit can be updated

1 : 1

Corresponding Px_DOUT[n] bit is protected

End of enumeration elements list.


P3_PMD

P3 I/O Mode Control
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_PMD P3_PMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P3_OFFD

P3 Digital Input Path Disable Control
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_OFFD P3_OFFD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P3_DOUT

P3 Data Output Value
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_DOUT P3_DOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P3_DMASK

P3 Data Output Write Mask
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_DMASK P3_DMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P3_PIN

P3 Pin Value
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_PIN P3_PIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P3_DBEN

P3 De-bounce Enable Control
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_DBEN P3_DBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P3_IMD

P3 Interrupt Mode Control
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_IMD P3_IMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P3_IEN

P3 Interrupt Enable Control
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_IEN P3_IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

P3_ISRC

P3 Interrupt Source Flag
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

P3_ISRC P3_ISRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.