\n

TMR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x20 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected

Registers

TCSR0

TCAP0

TEXCON0

TEXISR0

TCSR1

TCMPR1

TISR1

TDR1

TCAP1

TEXCON1

TEXISR1

TCMPR0

TISR0

TDR0


TCSR0

Timer0 Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCSR0 TCSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESCALE TDR_EN PERIODIC_SEL TOUT_PIN CAP_SRC WAKE_EN CTB CACT CRST MODE IE CEN DBGACK_TMR

PRESCALE : Prescale Counter\n
bits : 0 - 7 (8 bit)
access : read-write

TDR_EN : Data Load Enable Control\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer Data Register update Disabled

#1 : 1

Timer Data Register update Enabled while Timer counter is active

End of enumeration elements list.

PERIODIC_SEL : Periodic Mode Behavior Selection\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

In One-shot or Periodic mode, when write new TCMP, timer counter will reset

#1 : 1

In One-shot or Periodic mode, when write new TCMP if new TCMP TDR(current counter) , timer counter keep counting and will not reset. If new TCMP = TDR(current counter) , timer counter will reset

End of enumeration elements list.

TOUT_PIN : Toggle Out Pin Selection\nWhen Timer is set to toggle mode,\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time0/1 toggle output pin is T0/T1 pin

#1 : 1

Time0/1 toggle output pin is T0EX/T1EX pin

End of enumeration elements list.

CAP_SRC : Capture Pin Source Selection\n
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Capture Function source is from TxEX pin

#1 : 1

Capture Function source is from ACMPx output signal

End of enumeration elements list.

WAKE_EN : Wake-up Enable Control\nWhen WAKE_EN (UA_IER[6]) is set and the TIF or TEXIF (TEXISR[0]) is set, the timer controller will generator a wake-up trigger event to CPU.\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Wake-up trigger event Disabled

#1 : 1

Wake-up trigger event Enabled

End of enumeration elements list.

CTB : Counter Mode Enable Control\nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to section 6.12.5.3 for detail description.\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

External event counter mode Disabled

#1 : 1

External event counter mode Enabled

End of enumeration elements list.

CACT : Timer Active Status (Read Only)\nThis bit indicates the 24-bit up counter status.\n
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

#0 : 0

24-bit up counter is not active

#1 : 1

24-bit up counter is active

End of enumeration elements list.

CRST : Timer Reset\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Reset 8-bit prescale counter, 24-bit up counter value and CEN bit if CACT is 1

End of enumeration elements list.

MODE : Timer Operating Mode\n
bits : 27 - 28 (2 bit)
access : read-write

IE : Interrupt Enable Control\nIf this bit is enabled, when the timer interrupt flag (TIF) is set to 1, the timer interrupt signal is generated and inform to CPU.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer Interrupt function Disabled

#1 : 1

Timer Interrupt function Enabled

End of enumeration elements list.

CEN : Timer Enable Control\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Stops/Suspends counting

#1 : 1

Starts counting

End of enumeration elements list.

DBGACK_TMR : ICE Debug Mode Acknowledge Disable Control (Write Protect)\nTimer counter will keep going no matter CPU is held by ICE or not.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

ICE debug mode acknowledgement effects TIMER counting

#1 : 1

ICE debug mode acknowledgement Disabled

End of enumeration elements list.


TCAP0

Timer0 Capture Data Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TCAP0 TCAP0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCAP

TCAP : Timer Capture Data Register\nWhen TEXIF flag is set to 1, the current TDR value will be auto-loaded into this TCAP filed immediately.
bits : 0 - 23 (24 bit)
access : read-only


TEXCON0

Timer0 External Control Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEXCON0 TEXCON0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_PHASE TEX_EDGE TEXEN RSTCAPSEL TEXIEN TEXDB TCDB CAP_MODE

TX_PHASE : Timer External Count Pin Phase Detect Selection\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

A falling edge of Tx (x = 0~1) pin will be counted

#1 : 1

A rising edge of Tx (x = 0~1) pin will be counted

End of enumeration elements list.

TEX_EDGE : Timer External Pin Edge Detection\n
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 0

A 1 to 0 transition on TxEX (x = 0~1) will be detected

#01 : 1

A 0 to 1 transition on TxEX (x = 0~1) will be detected

#10 : 2

Either 1 to 0 or 0 to 1 transition on TxEX (x = 0~1) will be detected

#11 : 3

Reserved

End of enumeration elements list.

TEXEN : Timer External Pin Function Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

RSTCAPSEL function of TxEX (x = 0~1) pin will be ignored

#1 : 1

RSTCAPSEL function of TxEX (x = 0~1) pin is active

End of enumeration elements list.

RSTCAPSEL : Timer External Reset Counter / Timer External Capture Mode Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Transition on TxEX (x = 0~1) pin is using to save the TDR value into TCAP value if TEXIF flag is set to 1

#1 : 1

Transition on TxEX (x = 0~1) pin is using to reset the 24-bit up counter

End of enumeration elements list.

TEXIEN : Timer External Capture Interrupt Enable Control\nIf TEXIEN enabled, Timer will raise an external capture interrupt signal and inform to CPU while TEXIF flag is set to 1.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

TxEX (x = 0~1) pin detection Interrupt Disabled

#1 : 1

TxEX (x = 0~1) pin detection Interrupt Enabled

End of enumeration elements list.

TEXDB : Timer External Capture Input Pin De-bounce Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

TxEX (x = 0~1) pin de-bounce Disabled

#1 : 1

TxEX (x = 0~1) pin de-bounce Enabled

End of enumeration elements list.

TCDB : Timer External Counter Input Pin De-bounce Enable Control\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tx (x = 0~1) pin de-bounce Disabled

#1 : 1

Tx (x = 0~1) pin de-bounce Enabled

End of enumeration elements list.

CAP_MODE : Capture Mode Selection\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer counter reset function or free-counting mode of timer capture function

#1 : 1

Trigger-counting mode of timer capture function

End of enumeration elements list.


TEXISR0

Timer0 External Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEXISR0 TEXISR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEXIF

TEXIF : Timer External Interrupt Flag\nThis bit indicates the external capture interrupt flag status\nNote: This bit is cleared by writing 1 to it
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

TxEX (x = 0, 1) pin interrupt did not occur

#1 : 1

TxEX (x = 0, 1) pin interrupt occurred

End of enumeration elements list.


TCSR1

Timer1 Control and Status Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCSR1 TCSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TCMPR1

Timer1 Compare Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCMPR1 TCMPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TISR1

Timer1 Interrupt Status Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TISR1 TISR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TDR1

Timer1 Data Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TDR1 TDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TCAP1

Timer1 Capture Data Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCAP1 TCAP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TEXCON1

Timer1 External Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEXCON1 TEXCON1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TEXISR1

Timer1 External Interrupt Status Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEXISR1 TEXISR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TCMPR0

Timer0 Compare Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCMPR0 TCMPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCMP

TCMP : Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF flag will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.
bits : 0 - 23 (24 bit)
access : read-write


TISR0

Timer0 Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TISR0 TISR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF TWF

TIF : Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while TDR value reaches to TCMP value.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

TDR value matches the TCMP value

End of enumeration elements list.

TWF : Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of Time.\nNote: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer does not cause chip wake-up

#1 : 1

Chip wake-up from Idle or Power-down mode if Timer time-out interrupt signal generated

End of enumeration elements list.


TDR0

Timer0 Data Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TDR0 TDR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDR

TDR : Timer Data Register\nIf TDR_EN (TCSRx[16]) is set to 1, TDR register value will be updated continuously to monitor 24-bit up counter value.
bits : 0 - 23 (24 bit)
access : read-only



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