PPR

CNR1

CNR2

CNR3

CNR4

CNR5

CMR0

CMR1

CMR2

CMR3

CMR4

CMR5

CSR

PIER

PIIR

PWMPOE

PFBCON

PDZIR

TRGCON0

TRGCON1

TRGSTS0

TRGSTS1

PHCHG

PHCHGNXT

PCR

PHCHGMASK

INTACCUCTL

CNR0

CP01 : Clock Prescaler 0 For PWM Counter 0 And 1 Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM counter.
bits : 0 - 7 (8 bit)
access : read-write

CP23 : Clock Prescaler 2 For PWM Counter 2 And 3\nClock input is divided by (CP23 + 1) before it is fed to the corresponding PWM counter.\n
bits : 8 - 15 (8 bit)
access : read-write

CP45 : Clock Prescaler 4 For PWM Counter 4 And 5\nClock input is divided by (CP45 + 1) before it is fed to the corresponding PWM counter.\n
bits : 16 - 23 (8 bit)
access : read-write

CMRn : PWM Comparator Bits\nNote: Any write to CMRn will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

CSR0 : Timer 0 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
bits : 0 - 2 (3 bit)
access : read-write

CSR1 : Timer 1 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
bits : 4 - 6 (3 bit)
access : read-write

CSR2 : Timer 2 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
bits : 8 - 10 (3 bit)
access : read-write

CSR3 : Timer 3 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
bits : 12 - 14 (3 bit)
access : read-write

CSR4 : Timer 4 Clock Source Selection\nSelect clock input for PWM timer.\n(Table is the same as CSR5.)
bits : 16 - 18 (3 bit)
access : read-write

CSR5 : Timer 5 Clock Source Selection\nSelect clock input for PWM timer.\n
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMPIE0 : PWM Channel 0 Period Interrupt Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMPIE1 : PWM Channel 1 Period Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMPIE2 : PWM Channel 2 Period Interrupt Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMPIE3 : PWM Channel 3 Period Interrupt Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMPIE4 : PWM Channel 4 Period Interrupt Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMPIE5 : PWM Channel 5 Period Interrupt Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMDIE0 : PWM Channel 0 Duty Interrupt Enable Control\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMDIE1 : PWM Channel 1 Duty Interrupt Enable Control\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMDIE2 : PWM Channel 2 Duty Interrupt Enable Control\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMDIE3 : PWM Channel 3 Duty Interrupt Enable Control\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMDIE4 : PWM Channel 4 Duty Interrupt Enable Control\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMDIE5 : PWM Channel 5 Duty Interrupt Enable Control\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKIE : Fault Brake0 And 1 Interrupt Enable Control\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INT_TYPE : PWM Interrupt Type Selection Bit\nNote: This bit is effective when PWM in central align mode only.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMPIF0 : PWM Channel 0 Period Interrupt Flag\nFlag is set by hardware when PWM0 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

PWMPIF1 : PWM Channel 1 Period Interrupt Flag\nFlag is set by hardware when PWM1 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

PWMPIF2 : PWM Channel 2 Period Interrupt Flag\nFlag is set by hardware when PWM2 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

PWMPIF3 : PWM Channel 3 Period Interrupt Flag\nFlag is set by hardware when PWM3 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write

PWMPIF4 : PWM Channel 4 Period Interrupt Flag\nFlag is set by hardware when PWM4 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 4 - 4 (1 bit)
access : read-write

PWMPIF5 : PWM Channel 5 Period Interrupt Flag\nFlag is set by hardware when PWM5 down counter reaches zero. \nNote: Software can write 1 to clear this bit.
bits : 5 - 5 (1 bit)
access : read-write

PWMDIF0 : PWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when a channel 0 PWM counter reaches CMR0 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write

PWMDIF1 : PWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when a channel 1 PWM counter reaches CMR1 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 9 - 9 (1 bit)
access : read-write

PWMDIF2 : PWM Channel 2 Duty Interrupt Flag\nFlag is set by hardware when a channel 2 PWM counter reaches CMR2 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 10 - 10 (1 bit)
access : read-write

PWMDIF3 : PWM Channel 3 Duty Interrupt Flag\nFlag is set by hardware when a channel 3 PWM counter reaches CMR3 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 11 - 11 (1 bit)
access : read-write

PWMDIF4 : PWM Channel 4 Duty Interrupt Flag\nFlag is set by hardware when a channel 4 PWM counter reaches CMR4 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 12 - 12 (1 bit)
access : read-write

PWMDIF5 : PWM Channel 5 Duty Interrupt Flag\nFlag is set by hardware when a channel 5 PWM counter reaches CMR5 in down-count direction. \nNote: Software can write 1 to clear this bit.
bits : 13 - 13 (1 bit)
access : read-write

BKF0 : PWM Brake0 Flag\nNote: Software can write 1 to clear this bit.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKF1 : PWM Brake1 Flag\nNote: Software can write 1 to clear this bit.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0 : PWM Channel 0 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1 : PWM Channel 1 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM2 : PWM Channel 2 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM3 : PWM Channel 3 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM4 : PWM Channel 4 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM5 : PWM Channel 5 Output Enable Control\nNote: The corresponding GPIO pin must be switched to PWM function.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKEN0 : Enable BKP0 Pin Trigger Fault Brake Function 0\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKEN1 : Enable BKP1 Pin Trigger Fault Brake Function 1\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPO0BKEN : BKP1 Fault Brake Function Source Selection\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPO1BKEN : BKP0 Fault Brake Function Source Selection\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BKF : PWM Fault Brake Event Flag (Write 1 Clear)\nSoftware can write 1 to clear this bit and must clear this bit before restart PWM counter.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMBKO0 : PWM Channel 0 Brake Output Select Bit\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMBKO1 : PWM Channel 1 Brake Output Select Bit\n
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMBKO2 : PWM Channel 2 Brake Output Select Bit\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMBKO3 : PWM Channel 3 Brake Output Select Bit\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMBKO4 : PWM Channel 4 Brake Output Select Bit\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMBKO5 : PWM Channel 5 Brake Output Select Bit\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D6BKO6 : D6 Brake Output Select Bit\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D7BKO7 : D7 Brake Output Select Bit\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DZI01 : Dead-zone Interval Register For Pair Of Channel0 And Channel1 (PWM0 And PWM1 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.
bits : 0 - 7 (8 bit)
access : read-write

DZI23 : Dead-zone Interval Register For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.
bits : 8 - 15 (8 bit)
access : read-write

DZI45 : Dead-zone Interval Register For Pair Of Channel4 And Channel5 (PWM4 And PWM5 Pair)\nThese 8 bits determine dead-zone length.\nThe unit time of dead-zone length is received from corresponding CSR bits.
bits : 16 - 23 (8 bit)
access : read-write

CM0TRGREN : Enable PWM Trigger ADC Function While Channel0's Counter Matching CMR0 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNT0TRGEN : Enable PWM Trigger ADC Function While Channel0's Counter Matching CNR0\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CM0TRGFEN : Enable PWM Trigger ADC Function While Channel0's Counter Matching CMR0 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P0TRGEN : Enable PWM Trigger ADC Function While Channel0's Counter Matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CM1TRGREN : Enable PWM Trigger ADC Function While Channel1's Counter Matching CMR1 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNT1TRGEN : Enable PWM Trigger ADC Function While Channel1's Counter Matching CNR1\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CM1TRGFEN : Enable PWM Trigger ADC Function While Channel1's Counter Matching CMR1 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P1TRGEN : Enable PWM Trigger ADC Function While Channel1's Counter Matching 0 \nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CM2TRGREN : Enable PWM Trigger ADC Function While Channel2's Counter Matching CMR2 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNT2TRGEN : Enable PWM Trigger ADC Function While Channel2's Counter Matching CNR2\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CM2TRGFEN : Enable PWM Trigger ADC Function While Channel2's Counter Matching CMR2 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P2TRGEN : Enable PWM Trigger ADC Function While Channel2's Counter Matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CM3TRGREN : Enable PWM Trigger ADC Function While Channel3's Counter Matching CMR3 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNT3TRGEN : Enable PWM Trigger ADC Function While Channel3's Counter Matching CNR3\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CM3TRGFEN : Enable PWM Trigger ADC Function While Channel3's Counter Matching CMR3 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P3TRGEN : Enable PWM Trigger ADC Function While Channel3's Counter Matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CM4TRGREN : Enable PWM Trigger ADC Function While Channel4's Counter Matching CMR4 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNT4TRGEN : Enable PWM Trigger ADC Function While Channel4's Counter Matching CNR4\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CM4TRGFEN : Enable PWM Trigger ADC Function While Channel4's Counter Matching CMR4 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P4TRGEN : Enable PWM Trigger ADC Function While Channel4's Counter Matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CM5TRGREN : Enable PWM Trigger ADC Function While Channel5's Counter Matching CMR5 In Up-count Direction\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNT5TRGEN : Enable PWM Trigger ADC Function While Channel5's Counter Matching CNR5\nNote: This bit is only valid for PWM in center aligned mode. When PWM is in edged aligned mode, setting this bit is meaningless and will not take any effect.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CM5TRGFEN : Enable PWM Trigger ADC Function While Channel5's Counter Matching CMR5 In Down-count Direction\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P5TRGEN : Enable PWM Trigger ADC Function While Channel5's Counter Matching 0\nNote: This bit is valid for both center aligned mode and edged aligned mode.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMR0FLAG_R : ADC Trigger Flag By Counting Up To CMR\nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

CNT0FLAG : ADC Trigger Flag By Counting To CNR Note: Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

CMR0FLAG_F : ADC Trigger Flag By Counting Down To CMR\nNote: Software can write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

PERID0FLAG : ADC Trigger Flag By Period \nNote: Software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write

CMR1FLAG_R : ADC Trigger Flag By Counting Up To CMR\nNote: Software can write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write

CNT1FLAG : ADC Trigger Flag By Counting To CNR Note: Software can write 1 to clear this bit.
bits : 9 - 9 (1 bit)
access : read-write

CMR1FLAG_F : ADC Trigger Flag By Counting Down To CMR\nNote: Software can write 1 to clear this bit.
bits : 10 - 10 (1 bit)
access : read-write

PERID1FLAG : ADC Trigger Flag By Period \nNote: Software can write 1 to clear this bit.
bits : 11 - 11 (1 bit)
access : read-write

CMR2FLAG_R : ADC Trigger Flag By Counting Up To CMR \nNote: Software can write 1 to clear this bit.
bits : 16 - 16 (1 bit)
access : read-write

CNT2FLAG : ADC Trigger Flag By Counting To CNR Note: Software can write 1 to clear this bit.
bits : 17 - 17 (1 bit)
access : read-write

CMR2FLAG_F : ADC Trigger Flag By Counting Down To CMR\nNote: Software can write 1 to clear this bit.
bits : 18 - 18 (1 bit)
access : read-write

PERID2FLAG : ADC Trigger Flag By Period \nNote: Software can write 1 to clear this bit.
bits : 19 - 19 (1 bit)
access : read-write

CMR3FLAG_R : When Counter Counting Up To CMR, This Bit Will Be Set For Trigger ADC\nNote: Software can write 1 to clear this bit.
bits : 24 - 24 (1 bit)
access : read-write

CNT3FLAG : When Counter Counting To CNR, This Bit Will Be Set For Trigger ADC\nNote: Software can write 1 to clear this bit.
bits : 25 - 25 (1 bit)
access : read-write

CMR3FLAG_F : When Counter Counting Down To CMR, This Bit Will Be Set For Trigger ADC\nNote: Software can write 1 to clear this bit.
bits : 26 - 26 (1 bit)
access : read-write

PERID3FLAG : When Counter Counting To Period, This Bit Will Be Set For Trigger ADC \nNote: Software can write 1 to clear this bit.
bits : 27 - 27 (1 bit)
access : read-write

CMR4FLAG_R : ADC Trigger Flag By Counting Up To CMR\nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

CNT4FLAG : ADC Trigger Flag By Counting To CNR\nNote: Software can write 1 to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

CMR4FLAG_F : ADC Trigger Flag By Counting Down To CMR\nNote: Software can write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

PERID4FLAG : ADC Trigger Flag By Period \nNote: Software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write

CMR5FLAG_R : ADC Trigger Flag By Counting Up To CMR\nNote: Software can write 1 to clear this bit.
bits : 8 - 8 (1 bit)
access : read-write

CNT5FLAG : ADC Trigger Flag By Counting To CNR\nNote: Software can write 1 to clear this bit.
bits : 9 - 9 (1 bit)
access : read-write

CMR5FLAG_F : ADC Trigger Flag By Counting Down To CMR\nNote: Software can write 1 to clear this bit.
bits : 10 - 10 (1 bit)
access : read-write

PERID5FLAG : ADC Trigger Flag By Period \nNote: Software can write 1 to clear this bit.
bits : 11 - 11 (1 bit)
access : read-write

D0 : D0: When PWM0 Is Zero, Channel 0's Output Waveform Is D0\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D1 : D1: When PWM1 Is Zero, Channel 1's Output Waveform Is D1\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D2 : D2: When PWM2 Is Zero, Channel 2's Output Waveform Is D2\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D3 : D3: When PWM3 Is Zero, Channel 3's Output Waveform Is D3\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D4 : D4: When PWM4 Is Zero, Channel 4's Output Waveform Is D4\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D5 : D5: When PWM5 Is Zero, Channel 5's Output Waveform Is D5\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D6 : D6: When MASK6 Is 1, Channel 6's Output Waveform Is D6\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D7 : D7: When MASK7 Is 1, Channel 7's Output Waveform Is D7\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0 : PWM Channel 0 Output Enable Control\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1 : PWM Channel 1 Output Enable Control\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM2 : PWM Channel 2 Output Enable Control\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM3 : PWM Channel 3 Output Enable Control\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM4 : PWM Channel 4 Output Enable Control\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM5 : PWM Channel 5 Output Enable Control\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACCNT0 : Hardware Auto Clear CE0 When ACMP0 Trigger It\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACCNT1 : Hardware Auto Clear CE1 When ACMP1 Trigger It\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH01TOFF1 : Setting This Bit Will Force PWM0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: only for PWM0,PWM1,PWM2,PWM3.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH11TOFF1 : Setting This Bit Will Force PWM1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH21TOFF1 : Setting This Bit Will Force PWM2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH31TOFF1 : Setting This Bit Will Force PWM3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMP1SEL : CMP1SEL\nSelect the positive input source of ACMP1.\n
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

T1 : Timer1 Trigger PWM Function Enable Control\nWhen this bit is set, timer1 time-out event will update PHCHG with PHCHG_NXT register.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CE1 : ACMP1 Trigger Function Enable Control\nNote: This bit will be auto cleared when ACMP1 trigger PWM if ACCNT1 is set.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH01TOFF0 : Setting This Bit Will Force PWM0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH11TOFF0 : Setting This Bit Will Force PWM1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH21TOFF0 : Setting This Bit Will Force PWM2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH31TOFF0 : Setting This Bit Will Force PWM3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMP0SEL : CMP0SEL\nSelect the positive input source of ACMP0.\n
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

T0 : Timer0 Trigger PWM Function Enable Control\nWhen this bit is set, timer0 time-out event will update PHCHG with PHCHG_NXT register.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CE0 : ACMP0 Trigger Function Enable Control\nNote: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D0 : D0: When PWM0 Is Zero, Channel 0's Output Waveform Is D0\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D1 : D1: When PWM1 Is Zero, Channel 1's Output Waveform Is D1\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D2 : D2: When PWM2 Is Zero, Channel 2's Output Waveform Is D2\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D3 : D3: When PWM3 Is Zero, Channel 3's Output Waveform Is D3\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D4 : D4: When PWM4 Is Zero, Channel 4's Output Waveform Is D4\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D5 : D5: When PWM5 Is Zero, Channel 5's Output Waveform Is D5\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D6 : D6: When MASK6 Is 1, Channel 6's Output Waveform Is D6\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

D7 : D7: When MASK7 Is 1, Channel 7's Output Waveform Is D7\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0 : PWM Channel 0 Output Enable Control\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1 : PWM Channel 1 Output Enable Control\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM2 : PWM Channel 2 Output Enable Control\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM3 : PWM Channel 3 Output Enable Control\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM4 : PWM Channel 4 Output Enable Control\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM5 : PWM Channel 5 Output Enable Control\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACCNT0 : Hardware Auto Clear CE0 When ACMP0 Trigger It\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACCNT1 : Hardware Auto Clear CE1 When ACMP1 Trigger It\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH01TOFF1 : Setting This Bit Will Force PWM0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: only for PWM0,PWM1,PWM2,PWM3.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH11TOFF1 : Setting This Bit Will Force PWM1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH21TOFF1 : Setting This Bit Will Force PWM2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH31TOFF1 : Setting This Bit Will Force PWM3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP1 Trigger It This Feature Is Usually In Step Motor Application Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMP1SEL : CMP1SEL\nSelect the positive input source of ACMP1.\n
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

T1 : Timer1 Trigger PWM Function Enable Control\nWhen this bit is set, timer1 time-out event will update PHCHG with PHCHG_NXT register.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CE1 : ACMP1 Trigger Function Enable Control\nNote: This bit will be auto cleared when ACMP1 trigger PWM if ACCNT1 is set.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH01TOFF0 : Setting This Bit Will Force PWM0 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH11TOFF0 : Setting This Bit Will Force PWM1 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH21TOFF0 : Setting This Bit Will Force PWM2 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH31TOFF0 : Setting This Bit Will Force PWM3 To Output Low Lasting For At Most One Period Cycle As Long As ACMP0 Trigger It This Feature Is Usually In Step Motor Application Note: Only for PWM0, PWM1, PWM2, PWM3.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMP0SEL : CMP0SEL\nSelect the positive input source of ACMP0.\n
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

T0 : Timer0 Trigger PWM Function Enable Control\nWhen this bit is set, timer0 time-out event will update PHCHG with PHCHG_NXT register.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CE0 : ACMP0 Trigger Function Enable Control\nNote: This bit will be auto cleared when ACMP0 trigger PWM if ACCNT0 is set.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0EN : PWM-timer 0 Enable/Disable Start Run\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DB_MODE : PWM Debug Mode Configuration Bit (Available In DEBUG Mode Only)\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0INV : PWM-timer 0 Output Inverter Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0MOD : PWM-timer 0 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR0 and CMR0 cleared.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1EN : PWM-timer 1 Enable/Disable Start Run\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1INV : PWM-timer 1 Output Inverter ON/OFF\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1MOD : PWM-timer 1 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR1 and CMR1 cleared.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2EN : PWM-timer 2 Enable/Disable Start Run\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2INV : PWM-timer 2 Output Inverter Enable Control\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2MOD : PWM-timer 2 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR2 and CMR2 cleared.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH3EN : PWM-timer 3 Enable/Disable Start Run\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH3INV : PWM-timer 3 Output Inverter Enable Control\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH3MOD : PWM-timer 3 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR3 and CMR3 cleared.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH4EN : PWM-timer 4 Enable/Disable Start Run\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH4INV : PWM-timer 4 Output Inverter Enable Control\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH4MOD : PWM-timer 4 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR4 and CMR4 cleared.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH5EN : PWM-timer 5 Enable/Disable Start Run\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH5INV : PWM-timer 5 Output Inverter Enable Control\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH5MOD : PWM-timer 5 Auto-reload/One-shot Mode\nNote: If there is a rising transition at this bit, it will cause CNR5 and CMR5 cleared.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DZEN01 : Dead-zone 0 Generator Enable Control (PWM0 And PWM1 Pair For PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM0 and PWM1 becomes a complementary pair for PWM group.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DZEN23 : Dead-zone 2 Generator Enable Control (PWM2 And PWM3 Pair For PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM2 and PWM3 becomes a complementary pair for PWM group.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DZEN45 : Dead-zone 4 Generator Enable Control (PWM4 And PWM5 Pair For PWM Group)\nNote: When the dead-zone generator is enabled, the pair of PWM4 and PWM5 becomes a complementary pair for PWM group.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLRPWM : Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMMOD : PWM Operating Mode Selection\n
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GRP : Group Bit\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMTYPE : PWM Aligned Type Selection Bit\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MASK6 : MASK For D6
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MASK7 : MASK For D7
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPMASK0 : MASK For ACMP0 Note: Register CMP0CR is describe in Comparator Controller chapter
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPMASK1 : MASK For ACMP1\nNote: Register CMP1CR is describe in Comparator Controller chapter
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTACCUEN0 : Interrupt Accumulation Function Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PERIODCNT : Interrupt Accumulation Bits\nWhen INTACCUEN0 is set, PERIODCNT will decrease when every PWMPIF0 flag is set and when PERIODCNT reach to zero, the PWM0 interrupt will occurred and PERIODCNT will reload itself.
bits : 4 - 7 (4 bit)
access : read-write

CNRn : PWM Counter/Timer Loaded Value\nNote: Any write to CNRn will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write