I2CON

I2CLK

I2CTOC

I2CADDR1

I2CADDR2

I2CADDR3

I2CADM0

I2CADM1

I2CADM2

I2CADM3

I2CCON2

I2CADRR0

I2CADDR0

I2CSTATUS2

I2CDAT

I2CSTATUS

AA : Assert Acknowledge Control Bit\n
bits : 2 - 2 (1 bit)
access : read-write

SI : I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON[7]) is set, the I2C interrupt is requested. SI must be cleared by software. Software can write 1 to clear this bit.
bits : 3 - 3 (1 bit)
access : read-write

STO : I2C STOP Control Bit In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the Slave receiver mode to receive data from the master transmit device.
bits : 4 - 4 (1 bit)
access : read-write

STA : I2C START Control Bit\nSetting STA to logic 1 to enter Master mode. I2C hardware sends a START or repeats the START condition to bus when the bus is free.
bits : 5 - 5 (1 bit)
access : read-write

ENS1 : I2C Controller Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EI : Interrupt Enable Control\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2CLK : I2C Clock Divided Bits\nNote: The minimum value of I2CLK is 4.
bits : 0 - 7 (8 bit)
access : read-write

TIF : Time-out Flag\nThis bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.\nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

DIV4 : Time-out Counter Input Clock Divided By 4 Note: When enabled, the time-out period is extended 4 times.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENTI : Time-out Counter Enable Control\nNote: When the 14-bit time-out counter is enabled, it will start counting when SI is clear. Setting 1to the SI flag will reset counter and re-start up counting after SI is cleared.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2CADM : I2C Address Mask Bits\n
bits : 1 - 7 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKEUPEN : Wake-up Enable Control The system can be wake-up by I2C bus when the system is set into power mode and the received data matched one of the addresses in Address Register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TWOFF_EN : TWO LEVEL FIFO Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NOSTRETCH : NO STRETCH The I2C BUS\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVER_INTEN : I2C OVER RUN Interrupt Control Bit Setting OVER_INTEN to enable will send a interrupt to system when the TWOFF bit is enabled and there is over run event in received FIFO.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UNDER_INTEN : I2C UNDER RUN Interrupt Control Bit\nSetting UNDER_INTEN to enable will send a interrupt to system when the TWOFF bit is enabled and there is under run event happened in transmitted FIFO.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GC : General Call Function\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2CADDR : I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the MCU's own address. The I2C hardware will react if either of the address is matched.
bits : 1 - 7 (7 bit)
access : read-write

WAKEUPIF : I2C Wake-up Interrupt Flag\nWhen chip is woken up from Power-Down mode by I2C, this bit is set to 1. Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

FULL : I2C TWO LEVEL FIFO FULL\n
bits : 1 - 1 (1 bit)
access : read-write

EMPTY : I2C TWO LEVEL FIFO EMPTY\n
bits : 2 - 2 (1 bit)
access : read-write

OVERUN : I2C OVER RUN Status Bit
bits : 3 - 3 (1 bit)
access : read-write

UNDERUN : I2C UNDER RUN Status Bit
bits : 4 - 4 (1 bit)
access : read-write

I2CDAT : I2C Data Bits\nBit [7:0] is located with the 8-bit transferred data of the I2C serial port.
bits : 0 - 7 (8 bit)
access : read-write

I2CSTATUS : I2C Status Bits\n
bits : 0 - 7 (8 bit)
access : read-only