Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
SPI Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GO_BUSY : SPI Transfer Control Bit And Busy Status\nIf FIFO mode is enabled, this bit will be controlled by hardware and is Read only.\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNote 1: When FIFO mode is disabled, all configurations should be ready before writing 1 to the GO_BUSY bit.\nNote 2: In SPI Slave mode, if FIFO mode is disabled and the SPI bus clock is kept at idle state during a data transfer, the GO_BUSY bit will not be cleared to 0 when slave select signal goes to inactive state.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit to stop data transfer if SPI is transferring
#1 : 1
In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
End of enumeration elements list.
RX_NEG : Receive On Negative Edge\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The received data input signal latched on the Rising edge of SPICLK
#1 : 1
The received data input signal latched on the Falling edge of SPICLK
End of enumeration elements list.
TX_NEG : Transmit On Negative Edge\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transmitted data output signal is driven on the Rising edge of SPICLK
#1 : 1
The transmitted data output signal is driven on the Falling edge of SPICLK
End of enumeration elements list.
TX_BIT_LEN : Transmit Bit Length\nThis field specifies how many bits are transmitted in one transmit/receive. The minimum bit length is 8 bits and can up to 32 bits.\n
bits : 3 - 7 (5 bit)
access : read-write
LSB : LSB First\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB is transmitted/received first
#1 : 1
The LSB is transmitted/received first
End of enumeration elements list.
CLKP : Clock Polarity\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPICLK idle low
#1 : 1
SPICLK idle high
End of enumeration elements list.
SP_CYCLE : Suspend Interval (Master Only)
The four bits provide configurable suspend interval between two successive transactions in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation:
(SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle
Example:
bits : 12 - 15 (4 bit)
access : read-write
IF : Unit-transfer Interrupt Flag
Note 1: This bit will be cleared by writing 1 to itself.
Note 2: It's a mutual mirror bit of SPI_STATUS[16].
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transfer does not finish yet
#1 : 1
The SPI controller has finished one unit transfer
End of enumeration elements list.
IE : Unit-transfer Interrupt Enable Control\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI unit-transfer interrupt Disabled
#1 : 1
SPI unit-transfer interrupt Enabled
End of enumeration elements list.
SLAVE : Slave Mode Control\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
REORDER : Byte Reorder Function\nNote: This setting is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Byte reorder function Disabled
#1 : 1
Byte reorder function Enabled
End of enumeration elements list.
FIFO : FIFO Mode Enable Control
Note 1: Before enabling FIFO mode, the other related settings should be set in advance.
Note 2: In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data into the 4-depth transmit FIFO. When all data stored at transmit FIFO buffer are transferred, the GO_BUSY bit will back to 0.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
FIFO Mode Disabled
#1 : 1
FIFO Mode Enabled
End of enumeration elements list.
RX_EMPTY : Receive FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CNTRL[24].
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
The receive FIFO buffer is not empty
#1 : 1
The receive FIFO buffer is empty
End of enumeration elements list.
RX_FULL : Receive FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STATUS[25]
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
The receive FIFO buffer is not full
#1 : 1
The receive FIFO buffer is full
End of enumeration elements list.
TX_EMPTY : Transmit FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STAUTS[26].
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
The transmit FIFO buffer is not empty
#1 : 1
The transmit FIFO buffer is empty
End of enumeration elements list.
TX_FULL : Transmit FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_STATUS[27].
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
The transmit FIFO buffer is not full
#1 : 1
The transmit FIFO buffer is full
End of enumeration elements list.
SPI Data Receive Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Bits (Read Only)\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, bit RX [7:0] holds the received data. The values of the other bits are unknown.
bits : 0 - 31 (32 bit)
access : read-only
SPI Data Transmit Register
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Bits (Write Only)\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bit TX [7:0] will be transmitted in next transfer.
bits : 0 - 31 (32 bit)
access : write-only
SPI Control and Status Register 2
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NOSLVSEL : Slave 3-wire Mode Enable Control (Slave Only)
The SPI controller work with 3-wire interface including SPICLK, SPI_MISO, and SPI_MOSI
Note: In Slave 3-wire mode, the SS_LTRIG bit (SPI_SSR[4]) shall be set as 1.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The controller is 4-wire bi-direction interface
#1 : 1
The controller is 3-wire bi-direction interface in Slave mode. The controller will be ready to transmit/receive data after the GO_BUSY bit is set to 1
End of enumeration elements list.
SLV_ABORT : Slave 3-wire Mode Abort Control Bit (Slave Only)\nIn normal operation, there is an interrupt event when the number of received bits meets the requirement which defined in TX_BIT_LEN.\nIf the number of received bits is less than the requirement and there is no more bus clock input over one transfer time in Slave 3-wire mode, user can set this bit to force the current transfer done and then user can get a unit transfer interrupt event. \nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No force the transfer done when the NOSLVSEL bit is set to 1
#1 : 1
Force the transfer done when the NOSLVSEL bit is set to 1
End of enumeration elements list.
SSTA_INTEN : Slave 3-wire Mode Start Interrupt Enable Control (Slave Only)\nIt is used to enable interrupt when the transfer has started in slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, user can set the SLV_ABORT bit to force the transfer done.\nNote: It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared to 0.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transaction start interrupt Disabled
#1 : 1
Transaction start interrupt Enabled
End of enumeration elements list.
SLV_START_INTSTS : Slave 3-wire Mode Start Interrupt Status (Slave Only)
This bit dedicates if a transaction has started in slave 3-wire mode.
Note 1: It will be cleared automatically when a transaction is done or by writing 1 to this bit.
Note 2: It is a mutual mirror bit of SPI_STATUS[11].
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave does not detect any SPI bus clock transfer since the SSTA_INTEN bit was set to 1
#1 : 1
The transfer has started in slave 3-wire mode.
End of enumeration elements list.
SS_INT_OPT : Slave Select Inactive Interrupt Option (Slave Only)\nNote: This setting is only available if the SPI controller is configured as level trigger in slave device.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#1 : 1
As the slave select signal goes to inactive level, the IF bit will be set to 1
End of enumeration elements list.
BCn : Clock Configuration Backward Compatible Option\nNote: Refer to the description of SPI_DIVIDER register for details.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
The clock configuration is backward compatible
#1 : 1
The clock configuration is not backward compatible
End of enumeration elements list.
SPI Clock Divider Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER : Clock Divider Bits (Master Only)\nThe value in this field is the frequency divider to determine the SPI peripheral clock frequency fspi, and the SPI master's bus clock frequency on the SPICLK output pin. The frequency is obtained according to the following equation:\nIf the bit of BCn, SPI_CNTRL2[31], is set to 0.\n\nelse if BCn is set to 1,\n\nwhere \n is the SPI peripheral clock source which is defined in the CLKSEL1 register.
bits : 0 - 7 (8 bit)
access : read-write
SPI FIFO Control Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CLR : Clear Receive FIFO Buffer\nNote: This bit will be cleared to 0 by hardware after software sets it to 1 and the receive FIFO is cleared.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear receive FIFO buffer
End of enumeration elements list.
TX_CLR : Clear Transmit FIFO Buffer\nNote: This bit will be cleared to 0 by hardware after software sets it to 1 and the transmit FIFO is cleared.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear transmit FIFO buffer
End of enumeration elements list.
RX_INTEN : Receive Threshold Interrupt Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive threshold interrupt Disabled
#1 : 1
Receive threshold interrupt Enabled
End of enumeration elements list.
TX_INTEN : Transmit Threshold Interrupt Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit threshold interrupt Disabled
#1 : 1
Transmit threshold interrupt Enabled
End of enumeration elements list.
RXOV_INTEN : Receive FIFO Overrun Interrupt Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO overrun interrupt Disabled
#1 : 1
Receive FIFO overrun interrupt Enabled
End of enumeration elements list.
TIMEOUT_INTEN : Receive FIFO Time-out Interrupt Enable Control\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time-out interrupt Disabled
#1 : 1
Time-out interrupt Enabled
End of enumeration elements list.
RX_THRESHOLD : Received FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
bits : 24 - 25 (2 bit)
access : read-write
TX_THRESHOLD : Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
bits : 28 - 29 (2 bit)
access : read-write
SPI Status Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_INTSTS : Receive FIFO Threshold Interrupt Status (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#1 : 1
The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
End of enumeration elements list.
RX_OVERRUN : Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No overrun in receive FIFO
#1 : 1
Overrun in receive FIFO
End of enumeration elements list.
TX_INTSTS : Transmit FIFO Threshold Interrupt Status (Read Only)\n
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#1 : 1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
End of enumeration elements list.
SLV_START_INTSTS : Slave Start Interrupt Status (Slave Only)\nIt is used to dedicate that the transfer has started in slave 3-wire mode. \nNote 1: It will be cleared as transfer done or by writing one to this bit.\nNote 2: It's a mutual mirror bit of SPI_CNTRL2[11].
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave does not detect any SPI bus clock transfer since the SSTA_INTEN bit was set to 1
#1 : 1
The transfer has started in slave 3-wire mode
End of enumeration elements list.
RX_FIFO_COUNT : Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer.
bits : 12 - 15 (4 bit)
access : read-only
IF : SPI Unit-transfer Interrupt Flag\nNote 1: This bit will be cleared by writing 1 to itself.\nNote 2: It's a mutual mirror bit of SPI_CNTRL[16].
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transfer does not finish yet
#1 : 1
The SPI controller has finished one unit transfer
End of enumeration elements list.
TIMEOUT : Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No receive FIFO time-out event
#1 : 1
The receive FIFO buffer is not empty and it does not be read over 64 SPI clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
End of enumeration elements list.
RX_EMPTY : Receive FIFO Buffer Empty Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CNTRL[24].
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
The receive FIFO buffer is not empty
#1 : 1
The receive FIFO buffer is empty
End of enumeration elements list.
RX_FULL : Receive FIFO Buffer Full Indicator (Read Only) \nNote: It's a mutual mirror bit of SPI_CNTRL[25].
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
The receive FIFO buffer is not full
#1 : 1
The receive FIFO buffer is full
End of enumeration elements list.
TX_EMPTY : Transmit FIFO Buffer Empty Indicator (Read Only) \nNote: It's a mutual mirror bit of SPI_CNTRL[26].
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
The transmit FIFO buffer is not empty
#1 : 1
The transmit FIFO buffer is empty
End of enumeration elements list.
TX_FULL : Transmit FIFO Buffer Full Indicator (Read Only)\nNote: It's a mutual mirror bit of SPI_CNTRL[27].
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
The transmit FIFO buffer is not full
#1 : 1
The transmit FIFO buffer is full
End of enumeration elements list.
TX_FIFO_COUNT : Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer.
bits : 28 - 31 (4 bit)
access : read-only
SPI Slave Select Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSR : Slave Select Control Bit (Master Only)\nIf AUTOSS bit is 0,\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the SPISS line to inactive state.\nKeep the SPISS line at inactive state
#1 : 1
Set the proper SPISS line to active state.\nSelect the SPISS line to be automatically driven to active state for the duration of transmission/reception, and will be driven to inactive state for the rest of the time. The active state of SPISS is specified in SS_LVL bit
End of enumeration elements list.
SS_LVL : Slave Select Active Level (Slave Only)\nIt defines the active status of slave select signal (SPISS).\nIf SS_LTRIG bit is 1:\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The slave select signal SPISS is active at Low-level.\nThe slave select signal SPISS is active at Falling-edge
#1 : 1
The slave select signal SPISS is active at High-level.\nThe slave select signal SPISS is active at Rising-edge
End of enumeration elements list.
AUTOSS : Automatic Slave Selection Function Enable Bit (Master Only)\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPISS pin signal will be asserted/de-asserted by setting /clearing SSR bit
#1 : 1
SPISS pin signal will be generated automatically, which means that slave select signal will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished
End of enumeration elements list.
SS_LTRIG : Slave Select Level Trigger Enable Bit (Slave Only)\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The input slave select signal is edge-trigger
#1 : 1
The input slave select signal is level-trigger
End of enumeration elements list.
LTRIG_FLAG : Level Trigger Flag (Read Only, Slave Only)
When the SS_LTRIG bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not.
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
The transaction number or the transferred bit length of one transaction does not meet the specified requirements
#1 : 1
The transaction number and the transferred bit length met the specified requirements which defined in TX_BIT_LEN
End of enumeration elements list.
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