ADDR

ADCR

ADCHER

ADCMPR0

ADCMPR1

ADSR

ADTDCR

ADSAMP

RSLT : A/D Conversion Result\nThis field contains conversion result of ADC.
bits : 0 - 9 (10 bit)
access : read-only

OVERRUN : Over Run Flag\nIf converted data in RSLT[9:0] has not been read before the new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after the ADDR register is read.
bits : 16 - 16 (1 bit)
access : read-only

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VALID : Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADDR register is read.
bits : 17 - 17 (1 bit)
access : read-only

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ADEN : A/D Converter Enable Control\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption.
bits : 0 - 0 (1 bit)
access : read-write

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ADIE : A/D Interrupt Enable Control\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.\n
bits : 1 - 1 (1 bit)
access : read-write

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TRGS : Hardware Trigger Source\nNote: Software should disable TRGEN and ADST before change TRGS.
bits : 4 - 5 (2 bit)
access : read-write

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TRGCOND : External Trigger Condition\nThis bit decides whether the external pin STADC trigger event is falling or raising edge. The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigger.\n
bits : 6 - 6 (1 bit)
access : read-write

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TRGEN : External Trigger Enable Control\nEnable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source.\n
bits : 8 - 8 (1 bit)
access : read-write

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ADST : A/D Conversion Start\nADST bit can be set to 1 from three sources: software or PWM trigger and external pin STADC. ADST will be cleared to 0 by hardware automatically after conversion complete.\n
bits : 11 - 11 (1 bit)
access : read-write

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CHEN0 : Analog Input Channel 0 Enable Control\nNote: If software enables more than one channel, the channel with the smallest number will be selected and the other enabled channels will be ignored.
bits : 0 - 0 (1 bit)
access : read-write

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CHEN1 : Analog Input Channel 1 Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

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CHEN2 : Analog Input Channel 2 Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

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CHEN3 : Analog Input Channel 3 Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

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CHEN4 : Analog Input Channel 4 Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write

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CHEN5 : Analog Input Channel 5 Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write

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CHEN6 : Analog Input Channel 6 Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write

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CHEN7 : Analog Input Channel 7 Enable Control\n
bits : 7 - 7 (1 bit)
access : read-write

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PRESEL : Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7, the ADC clock rate needs to be limited to lower than 300 kHz.
bits : 8 - 8 (1 bit)
access : read-write

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CMPEN : Compare Enable Control\nSet 1 to this bit to enable comparing CMPD[9:0] with specified channel conversion results when converted data is loaded into the ADDR register.\n
bits : 0 - 0 (1 bit)
access : read-write

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CMPIE : Compare Interrupt Enable Control\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.\n
bits : 1 - 1 (1 bit)
access : read-write

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CMPCOND : Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
bits : 2 - 2 (1 bit)
access : read-write

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CMPCH : Compare Channel Selection\n
bits : 3 - 5 (3 bit)
access : read-write

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CMPMATCNT : Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND, the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
bits : 8 - 11 (4 bit)
access : read-write

CMPD : Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel.
bits : 16 - 25 (10 bit)
access : read-write

ADF : A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. ADF is set to 1 When A/D conversion ends.\nSoftware can write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

CMPF0 : Compare Flag 0\nWhen the selected channel A/D conversion result meets the setting condition in ADCMPR0, this bit is set to 1. Software can write 1 to clear this bit to 0.\n
bits : 1 - 1 (1 bit)
access : read-write

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CMPF1 : Compare Flag 1\nWhen the selected channel A/D conversion result meets the setting condition in ADCMPR1, this bit is set to 1. Software can write 1 to clear this bit to 0.\n
bits : 2 - 2 (1 bit)
access : read-write

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BUSY : BUSY/IDLE (Read Only)\nThis bit is mirror of as ADST bit in ADCR\n
bits : 3 - 3 (1 bit)
access : read-only

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CHANNEL : Current Conversion Channel (Read Only)\n
bits : 4 - 6 (3 bit)
access : read-only

VALID : Data Valid Flag (Read Only)\nIt is a mirror of VALID (ADDR[17]) bit in ADDR register.
bits : 8 - 8 (1 bit)
access : read-only

OVERRUN : Overrun Flag (Read Only)\nIt is a mirror to OVERRUN (ADSR[16]) bit in ADDR register.
bits : 16 - 16 (1 bit)
access : read-only

PTDT : PWM Trigger Delay Timer\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * PTDT) * system clock.
bits : 0 - 7 (8 bit)
access : read-write

ADSAMPCNT : ADC Sampling Counter\nIf the ADC input is unstable, user can set this register to increase the sampling time to get a stable ADC input signal. The default sampling time is 1 ADC clock. The additional clock number will be inserted to lengthen the sampling clock.\n
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.