SYS_PDID (PDID)

SYS_REGLCTL (REGLCTL)

SYS_BODCTL (BODCTL)

SYS_P0_MFP (P0_MFP)

SYS_P1_MFP (P1_MFP)

SYS_P2_MFP (P2_MFP)

SYS_P3_MFP (P3_MFP)

SYS_RSTSTS (RSTSTS)

SYS_P4_MFP (P4_MFP)

SYS_P5_MFP (P5_MFP)

SYS_EINT0SEL (EINT0SEL)

SYS_IPRST0 (IPRST0)

SYS_IRCTCTL (IRCTCTL)

SYS_IRCTIEN (IRCTIEN)

SYS_IRCTISTS (IRCTISTS)

SYS_IPRST1 (IPRST1)

PDID : Product Device Identification Number\nThis register reflects the device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only

REGWRPROT : Register Write-Protection Disable Index (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REGPROTDIS : Register Write-Protection Code (Write Only)\nSome registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 0x59, 0x16, 0x88 to this field. After this sequence is completed, the REGWRPROT bit will be set to 1 and write-protection registers can be normal write.
bits : 0 - 7 (8 bit)
access : write-only

BODVL_EXT : Brown-Out Detector Selection Extension (Initiated Write-Protected Bit)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODVL1_0 : Brown-Out Detector Threshold Voltage Selection (Initiated Write-Protected Bit)
bits : 1 - 2 (2 bit)
access : read-write

BODRSTEN : Brown-Out Reset Enable (Initiated And Write-Protected Bit)\nThe default value is set by flash controller user configuration register config0 bit[20].\nWhen the BOREN is enabled and the interrupt is asserted, the interrupt will be kept till the BOREN is set to 0. The interrupt for CPU can be blocked by disabling the NVIC in CPU for BOD interrupt or disable the interrupt source by disabling the BOREN and then re-enabling the BOREN function if the BOD function is required.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODIF : Brown-Out Detector Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODLPM : Brown-Out Detector Low Power Mode (Write-Protected)\nThe BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODOUT : Brown-Out Detector Output State
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODVL2 : Brown-Out Detector Threshold Voltage Selection (Initiated Write-Protected Bit) The default value is set by flash controller user configuration register config0 bit[19].
bits : 7 - 7 (1 bit)
access : read-write

BOREN : Brown-Out Reset Enable\nThe bit will enable BOR reset function. When VDD5V lower than 1.7v BOR will reset whole chip.\n0: Disable\n1: Enable
bits : 8 - 8 (1 bit)
access : read-write

MFP : P0 Multiple Function Selection\nThe pin function of P0 depends on P0_MFP and ALT.\nRefer to ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

ALT0 : P0.0 Alternate Function Selection
bits : 8 - 8 (1 bit)
access : read-write

ALT1 : P0.1 Alternate Function Selection
bits : 9 - 9 (1 bit)
access : read-write

ALT4 : P0.4 Alternate Function Selection
bits : 12 - 12 (1 bit)
access : read-write

ALT5 : P0.5 Alternate Function Selection
bits : 13 - 13 (1 bit)
access : read-write

ALT6 : P0.6 Alternate Function Selection
bits : 14 - 14 (1 bit)
access : read-write

ALT7 : P0.7 Alternate Function Selection
bits : 15 - 15 (1 bit)
access : read-write

TYPE : P0[7:0] Input Schmitt Trigger Function Enable
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HS : P0[7:0] Slew Rate Control
bits : 24 - 31 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFP : P1 Multiple Function Selection\nThe pin function of P1 depends on MFP and ALT.\nRefer to P1_ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

ALT0 : P1.0 Alternate Function Selection
bits : 8 - 8 (1 bit)
access : read-write

ALT2 : P1.2 Alternate Function Selection
bits : 10 - 10 (1 bit)
access : read-write

ALT3 : P1.3 Alternate Function Selection
bits : 11 - 11 (1 bit)
access : read-write

ALT4 : P1.4 Alternate Function Selection
bits : 12 - 12 (1 bit)
access : read-write

ALT5 : P1.5 Alternate Function Selection
bits : 13 - 13 (1 bit)
access : read-write

ALT6 : P1.6 Alternate Function Selection
bits : 14 - 14 (1 bit)
access : read-write

TYPE : P1[7:0] Input Schmitt Trigger Function Enable
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HS : P1[7:0] Slew Rate Control
bits : 24 - 31 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFP : P2 Multiple Function Selection\nThe pin function of P2 depends on P2_MFP and ALT.\nRefer to ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

ALT2 : P2.2 Alternate Function Selection
bits : 10 - 10 (1 bit)
access : read-write

ALT3 : P2.3 Alternate Function Selection
bits : 11 - 11 (1 bit)
access : read-write

ALT4 : P2.4 Alternate Function Selection
bits : 12 - 12 (1 bit)
access : read-write

ALT5 : P2.5 Alternate Function Selection
bits : 13 - 13 (1 bit)
access : read-write

ALT6 : P2.6 Alternate Function Selection
bits : 14 - 14 (1 bit)
access : read-write

ALT7 : P2.7 Alternate Function Selection
bits : 15 - 15 (1 bit)
access : read-write

TYPE : P2[7:0] Input Schmitt Trigger Function Enable
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HS : P2[7:0] Slew Rate Control
bits : 24 - 31 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFP : P3 Multiple Function Selection\nThe pin function of P3 depends on MFP and ALT.\nRefer to ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

ALT0 : P3.0 Alternate Function Selection
bits : 8 - 8 (1 bit)
access : read-write

ALT1 : P3.1 Alternate Function Selection
bits : 9 - 9 (1 bit)
access : read-write

ALT2 : P3.2 Alternate Function Selection
bits : 10 - 10 (1 bit)
access : read-write

ALT4 : P3.4 Alternate Function Selection
bits : 12 - 12 (1 bit)
access : read-write

ALT5 : P3.5 Alternate Function Selection
bits : 13 - 13 (1 bit)
access : read-write

ALT6 : P3.6 Alternate Function Selection
bits : 14 - 14 (1 bit)
access : read-write

ALT7 : P3.7 Alternate Function Selection
bits : 15 - 15 (1 bit)
access : read-write

TYPE : P3[7:0] Input Schmitt Trigger Function Enable
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P32CTL : P3.2 Alternate Function Selection Extension
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HS : P3[6:0] Slew Rate Control
bits : 25 - 31 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PORF : Power-On Reset Flag The PORF flag is set by the reset signal , which is from the Power-On Reset (POR) controller or bit CHIPRST (SYS_IPRST0[0]), to indicate the previous reset source. Note: Software can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINRF : Reset Pin Reset Flag The PINRF flag is set by the reset signal from the /RESET pin to indicate the previous reset source. Note: Software can write 1 to clear this bit to zero.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTRF : Watchdog Reset Flag The RSTS_WDT flag is set by the reset signal from the Watchdog timer to indicate the previous reset source. Note: Software can write 1 to clear this bit to zero.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BODRF : Brown-Out Detector Reset Flag The BODRF flag is set by the reset signal from the Brown-out Detector to indicate the previous reset source. Note: Software can write 1 to clear this bit to zero.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRF : MCU Reset Flag The SYSRF flag is set by the reset signal from the Cortex-M0 core to indicate the previous reset source. Note: Software can write 1 to clear this bit to zero.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURF : CPU Reset Flag\nThe CPURF flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 core and Flash memory controller (FMC).\nNote: Software can write 1 to clear this bit to zero.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFP : P4 Multiple Function Selection\nThe pin function of P4 depends on MFP and P4_ALT.\nRefer to ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

ALT6 : P4.6 Alternate Function Selection
bits : 14 - 14 (1 bit)
access : read-write

ALT7 : P4.7 Alternate Function Selection
bits : 15 - 15 (1 bit)
access : read-write

TYPE : P4[7:0] Input Schmitt Trigger Function Enable
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HS : P4[7:0] Slew Rate Control
bits : 24 - 31 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFP : P5 Multiple Function Selection\nThe pin function of P5 depends on MFP and ALT.\nRefer to ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

ALT0 : P5.0 Alternate Function Selection
bits : 8 - 8 (1 bit)
access : read-write

ALT1 : P5.1 Alternate Function Selection
bits : 9 - 9 (1 bit)
access : read-write

ALT2 : P5.2 Alternate Function Selection
bits : 10 - 10 (1 bit)
access : read-write

ALT3 : P5.3 Alternate Function Selection
bits : 11 - 11 (1 bit)
access : read-write

ALT4 : P5.4 Alternate Function Selection
bits : 12 - 12 (1 bit)
access : read-write

ALT5 : P5.5 Alternate Function Selection
bits : 13 - 13 (1 bit)
access : read-write

TYPE : P5[7:0] Input Schmitt Trigger Function Enable
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HS : P5[7:0] Slew Rate Control
bits : 24 - 31 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEL : INT0 SEL GPB3
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHIPRST : CHIP One-Shot Reset (Write Protect)\nSetting this bit will reset the CHIP, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is the same as the POR reset, and all the chip module is reset and the chip settings from flash are also reload.\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGLCTL at address SYS_BA + 0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURST : CPU Kernel One Shot Reset\nSetting this bit will reset the CPU kernel, and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGLCTL at address SYS_BA + 0x100.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPUWS : CPU Wait-State Control For Flash Memory Access\n0: Insert one wait-state when access Flash\n1: Non-insert wait-state when access Flash\nNote: When HCLK frequency is faster than 44MHz, insert one wait state is necessary.
bits : 2 - 2 (1 bit)
access : read-write

FREQSEL : Trim Frequency Selection\nThis bit is to enable the HFIRC auto trim.\nWhen setting this bit to 1, the HFIRC auto trim function will trim HFIRC to 22.1184 MHz automatically based on the LXT reference clock.\nDuring auto trim operation, if LXT clock error is detected or trim retry limitation count reached, this field will be cleared to 0 automatically.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOOPSEL : Trim Calculation Loop This field defines trim value calculation based on the number of LXT clock. For example, if LOOPSEL is set as 00 , auto trim circuit will calculate trim value based on the average frequency difference in 4 LXT clock. This field also defines how many times the auto trim circuit will try to update the HFIRC trim value before the frequency of HFIRC is locked. Once the HFIRC is locked, the internal trim value update counter will be reset. If the trim value update counter reaches this limitation value and frequency of HFIRC is still not locked, the auto trim operation will be disabled and FREQSEL will be cleared to 0.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIEN : Trim Failure Interrupt Enable\nThis bit controls if an interrupt will be triggered while HFIRC trim value update limitation count is reached and HFIRC frequency is still not locked on target frequency set by FREQSEL.\nIf this bit is high and TFAILIF is set during auto trim operation, an interrupt will be triggered to notify that HFIRC trim value update limitation count is reached.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKEIEN : LXT Clock Error Interrupt Enable\nThis bit controls if CPU could get an interrupt while LXT clock is inaccurate during auto trim operation.\nIf this bit is high, and CLKERRIF is set during auto trim operation, an interrupt will be triggered to notify the LXT clock frequency is inaccurate.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQLOCK : HFIRC Frequency Lock Status\nThis bit indicates the HFIRC frequency locked in 22.1184 MHz.\nThis is a read only status bit and doesn't trigger any interrupt.
bits : 0 - 0 (1 bit)
access : read-write

TFAILIF : Trim Failure Interrupt Status\nThis bit indicates that HFIRC trim value update limitation count reached and HFIRC clock frequency still doesn't lock. Once this bit is set, the auto trim operation stopped and FREQSEL will be cleared to 0 by hardware automatically.\nIf this bit is set and TFAILIEN is high, an interrupt will be triggered to notify that HFIRC trim value update limitation count was reached. Software can write 1 to clear this bit to zero.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERRIF : LXT Clock Error Interrupt Status\nThis bit indicates that LXT clock frequency is inaccuracy. Once this bit is set, the auto trim operation stopped and FREQSEL will be cleared to 0 by hardware automatically.\nIf this bit is set and CLKEIEN is high, an interrupt will be triggered to notify the LXT clock frequency is inaccuracy. Software can write 1 to clear this bit to zero.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIORST : GPIO (P0~P5) Controller Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C_RST : I2C Controller Reset
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPIRST : SPI Controller Reset
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1RST : UART1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMRST : PWM Controller Reset
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMPRST : ACMP Controller Reset
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCRST : ADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.