CLK_PWRCTL (PWRCTL)

CLK_CLKSEL0 (CLKSEL0)

CLK_CLKSEL1 (CLKSEL1)

CLK_CLKDIV (CLKDIV)

CLK_CLKSEL2 (CLKSEL2)

CLK_CLKOCTL (CLKOCTL)

CLK_AHBCLK (AHBCLK)

CLK_APBCLK (APBCLK)

CLK_STATUS (STATUS)

XTLEN : External HXT Or LXT Crystal Oscillator Enable Control (Write Protect) The default clock source is from HIRC. These two bits are default set to 00 and the XTAL1 and XTAL2 pins are GPIO. Note: To enable external XTAL function, P5_ALT[1:0] and P5_MFP[1:0] bits must also be set in P5_MFP.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIRCEN : 44.2368 MHz Internal High Speed RC Oscillator (HIRC) Enable Control (Write Protect)\nNote: The default of HIRCEN bit is 1.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIRCEN : 10 KHz Internal Low Speed RC Oscillator (LIRC) Enable Control (Write Protest)
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDWKDLY : Wake-Up Delay Counter Enable Control (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz external high speed crystal (HXT), 4096 clock cycles for 32.768 kHz external low speed crystal (LXT), and 16 clock cycles when chip works at 22.1184 MHz internal high speed RC oscillator (HIRC).
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDWKIEN : Power-Down Mode Wake-Up Interrupt Enable Control (Write Protect)\nNote: The interrupt will occur when both PDWKIF and PDWKIEN are high.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDWKIF : Power-Down Mode Wake-Up Interrupt Status Set by Power-down wake-up event , which indicates that resume from Power-down mode The flag is set if the GPIO, UART, WDT, ACMP, Timer or BOD wake-up occurred. Note: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. Write 1 to clear the bit to 0.
bits : 6 - 6 (1 bit)
access : read-write

PDEN : System Power-Down Enable Bit (Write Protect)\nWhen chip wakes up from Power-down mode, this bit is cleared by hardware. User needs to set this bit again for next Power-down.\nIn Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT), 32.768 kHz external low speed crystal oscillator (LXT), and the 22.1184 MHz internal high speed oscillator (HIRC) will be disabled in this mode, and 10 kHz internal low speed RC oscillator (LIRC) are not controlled by Power-down mode.\nIn Power-down mode, the system clock is disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from 10 kHz internal low speed oscillator.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDLXT : Enable LXT In Power-Down Mode\nThis bit controls the crystal oscillator active or not in Power-down mode.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXTGAIN : HXT Gain Selection
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLKSEL : HCLK Clock Source Selection (Write Protect)\nNote1: Before clock switching, the related clock sources (both pre-select and new-select) must be turn-on and stable.\nNote2: These bits are protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address SYS_BA + 0x100.\nNote3: To set CLK_PWRCTL[1:0] to select HXT or LXT crystal clock.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STCLKSEL : Cortex-M0 SysTick Clock Source Selection From Reference Clock (Write Protect)\nNote3: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTSEL : WDT CLK Clock Source Selection (Write Protect)\nNote1: These bits are the protected bit, and programming them needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address SYS_BA + 0x100.\nNote2: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCSEL : ADC Peripheral Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPISEL : SPI Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0SEL : TIMER0 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1SEL : TIMER1 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0SEL : UART0 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1SEL : UART1 Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write

UART0DIV : UART0 Clock Divide Number From UART0 Clock Source
bits : 8 - 11 (4 bit)
access : read-write

UART1DIV : UART1 Clock Divide Number From UART1 Clock Source
bits : 12 - 15 (4 bit)
access : read-write

ADCDIV : ADC Peripheral Clock Divide Number From ADC Peripheral Clock Source
bits : 16 - 23 (8 bit)
access : read-write

FDIVSEL : Clock Divider Clock Source Selection\nNote: To set CLK_PWRCTL[1:0], select HXT or LXT crystal clock.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FSEL : Divider Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write

CLKOEN : Frequency Divider Enable Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIV1EN : Frequency Divider 1 Enable Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPCKEN : Flash ISP Controller Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HDIVEN : Divider Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTCKEN : Watchdog Timer Clock Enable Control (Write Protect)\nNote: This bit is the protected bit, and programming it needs to write 0x59, 0x16, and 0x88 to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address SYS_BA + 0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0CKEN : Timer0 Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1CKEN : Timer1 Clock Enable Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKOCKEN : Frequency Divider Output Clock Enable Control
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2CCKEN : I2C Clock Enable Control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPICKEN : SPI Peripheral Clock Enable Control
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0CKEN : UART0 Clock Enable Control
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1CKEN : UART1 Clock Enable Control
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMCH01CKEN : PWM_01 Clock Enable Control
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMCH23CKEN : PWM_23 Clock Enable Control
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMCH45CKEN : PWM_45 Clock Enable Control
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCCKEN : Analog-Digital-Converter (ADC) Clock Enable Control
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMPCKEN : Analog Comparator Clock Enable Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XTLSTB : HXT Or LXT Clock Source Stable Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIRCSTB : LIRC Clock Source Stable Flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HIRCSTB : HIRC Clock Source Stable Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CLKSFAIL : Clock Switch Fail Flag\nNote1: This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote2: This bit is read only. After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.