ADC_DAT (DAT)

ADC_CTL (CTL)

ADC_CHEN (CHEN)

ADC_CMP0 (CMP0)

ADC_CMP1 (CMP1)

ADC_STATUS (STATUS)

ADC_TRGDLY (TRGDLY)

ADC_EXTSMPT (EXTSMPT)

ADC_SEQCTL (SEQCTL)

ADC_SEQDAT0 (SEQDAT0)

ADC_SEQDAT1 (SEQDAT1)

RESULT : A/D Conversion Result\nThis field contains conversion result of ADC.
bits : 0 - 9 (10 bit)
access : read-only

OV : Over Run Flag\nIf converted data in RESULT[9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after the ADC_DAT register is read.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

VALID : Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

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ADCEN : A/D Converter Enable\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCIEN : A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADCIEN bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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HWTRGSEL : Hardware Trigger Source\nNote: Software should disable HWTRGEN and SWTRG before change HWTRGSEL.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HWTRGCOND : External Trigger Condition\nThis bit decides whether the external pin STADC trigger event is falling or raising edge. The signal must be kept at stable state at least 4 PCLKs at high and low state for edge trigger.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HWTRGEN : External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin. If external trigger is enabled, the SWTRG bit can be set to 1 by the selected hardware trigger source.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWTRG : A/D Conversion Start\nSWTRG bit can be set to 1 from two sources: software and external pin STADC. SWTRG will be cleared to 0 by hardware automatically after conversion complete.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VREFSEL : Reference Voltage Selection Signal
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

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CHEN0 : Analog Input Channel 0 Enable\nNote: If software enables more than one channel, the channel with the smallest number will be selected and the other enabled channels will be ignored.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN1 : Analog Input Channel 1 Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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CHEN2 : Analog Input Channel 2 Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

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CHEN3 : Analog Input Channel 3 Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

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CHEN4 : Analog Input Channel 4 Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

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CHEN5 : Analog Input Channel 5 Enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

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CHEN6 : Analog Input Channel 6 Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

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CHEN7 : Analog Input Channel 7 Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

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CH7SEL : Analog Input Channel 7 Selection\nNote: When software selects the band-gap voltage as the analog input source of ADC channel 7, the ADC clock rate needs to be limited to lower than 300 kHz.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

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CHEN8 : Analog Input Channel 8 Enable
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

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CHEN9 : Analog Input Channel 9 Enable
bits : 10 - 10 (1 bit)
access : read-write

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CHEN10 : Analog Input Channel 10 Enable
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

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CHEN11 : Analog Input Channel 11 Enable
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

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BGEN : Band-Gap Voltage Measurement\nNote: User can set BGEN high to use ADC to measure Band-Gap voltage directly to instead of enabling PRESET and CHEN7.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPEN : Compare Enable\nSet 1 to this bit to enable comparing CMPDAT[9:0] with specified channel conversion results when converted data is loaded into the ADC_DAT register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPIE : Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT, ADCMPFx bit will be asserted, in the meanwhile, if CMPCOND is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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CMPCOND : Compare Condition\nNote: When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFx bit will be set.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

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CMPCH : Compare Channel Selection
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

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CMPMCNT : Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFx bit will be set.
bits : 8 - 11 (4 bit)
access : read-write

CMPDAT : Comparison Data\nThe 10-bit data is used to compare with conversion result of specified channel.
bits : 16 - 25 (10 bit)
access : read-write

ADIF : A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. ADIF is set to 1 When A/D conversion ends.\nSoftware can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write

ADCMPF0 : Compare Flag 0\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP0, this bit is set to 1. Software can write 1 to clear this bit to zero.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPF1 : Compare Flag 1\nWhen the selected channel A/D conversion result meets the setting condition in ADC_CMP1, this bit is set to 1. Software can write 1 to clear this bit to zero.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

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BUSY : BUSY/IDLE (Read Only)\nThis bit is mirror of as SWTRG bit in ADC_CTL
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

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CHANNEL : Current Conversion Channel (Read Only)
bits : 4 - 6 (3 bit)
access : read-only

VALID : Data Valid Flag (Read Only)\nIt is a mirror of VALID bit in ADC_DAT register.
bits : 8 - 8 (1 bit)
access : read-only

OV : OV Flag (Read Only)\nIt is a mirror to OV bit in ADC_DAT register.
bits : 16 - 16 (1 bit)
access : read-only

DELAY : PWM Trigger Delay Timer\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * DELAY) * system clock.
bits : 0 - 7 (8 bit)
access : read-write

EXTSMPT : ADC Sampling Counter\nADC sampling counters are 6 ADC clock is suggestion.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEQEN : ADC Sequential Mode Enable\nWhen ADC sequential mode is enabled, two of three ADC channels from 0 to 2 will automatically convert analog data in the sequence of channel [0, 1] or channel[1, 2] or channel[0, 2] defined by SEQ_MODE[1:0].
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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SEQTYPE : ADC Sequential Mode Type
bits : 1 - 1 (1 bit)
access : read-write

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MODESEL : ADC Sequential Mode Selection
bits : 2 - 3 (2 bit)
access : read-write

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TRG1TYPE : ADC Sequential Mode Trigger1 Type
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

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TRG1SRC : ADC Sequential Mode Trigger1 Source
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

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TRG2TYPE : ADC Sequential Mode Trigger2 Type
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

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TRG2SRC : ADC Sequential Mode Trigger2 Source
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RESULT : A/D PWM Sequential Mode Conversion Result\nThis field contains conversion result of ADC.
bits : 0 - 9 (10 bit)
access : read-only

OV : Over Run Flag\nIf converted data in RESULT [9:0] has not been read before the new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after the ADC_DAT register is read.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

VALID : Valid Flag\nThis bit is set to 1 when ADC conversion is completed and cleared by hardware after the ADC_DAT register is read.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.